Here is my problem, Not sure what would be done to fix this problem.

If you have some IO at $D000 to $DFFF and you break out address A15, A14, !A13, A12 into a 74138 IC, and you have a ram access to E0DFFF it will also activate the 138 In fact any address that also ends in D000 to DFFF above $DFFF will turn the 138 on.

In Logic CE=A15,A14,A12 & !A13, A16 to A23. I was thinking of a 13to1 NAND but I suppose its really going to slow things down.

I am amazed when using Xilinx CPLD's/FPGA's. You put a few logic gates in series and would expect the delay rating for the IC to add up (in my case 7.5nS). But it doesn't. I use a 7 input NOR gate in series with an OR gate for a certain address decode. The observed delay on the scope is still 7.5nS.

If you can design on Eagle, you can design with Xilinx ISE. You will need to register/download their software, buy one of their IC's, maybe an adapter socket too. Also buy a JTAG cable to program it.

It may sound intimidating at first, but with their software, JTAG cable, and an IC, you will begin to realize the full potential of programmable logic, cheap! Some say you need to learn VHDL/Verilog. But for simple address decoding, schematic entry is "relatively" easy to a seasoned hobbyist.

If you are interested in this path I would recommend some of Xilinx's .pdf's

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Another option might be to use a smaller programmable device to serve as the decoder.

The Lattice 16V8D GAL chips are available in 20 pin DIP with speeds as fast as 7.5ns. These can be purchased from Mouser for $2.44 each.
The larger 22V10D in a 24 pin DIP and 10ns for $5.42. Faster versions are in 28 pin PLCC.

I will program the DIP parts for free for anyone interested - I only ask for you to cover the return postage.

As part of the "consortium" Garth mentioned here: viewtopic.php?t=1656&start=52 , I am considering offering a pre-programmed 16V8D or 22V10D that offers a standard memory map using 32k SRAM, 32K EPROM, and has several IO device selects. It will also have the the /MRD and /MWR signals gated from R/W and PHI2. This will remove the need for descrete glue logic and provide a simple building block for beginners and advanced designers too.

For 65816 users, a 9536 CPLD (44 pin PLCC package) will have the Bank select register along with memory and I/O device selects to allow for larger memory map usage.

I am still developing these items, but if you are interested, drop me an email and we can discuss it further.

Daryl

This is because most FPGAs implement their logic with look-up tables in SRAM. The programmer is converting your explicit schematics into an equivalent truth-table, and storing the truth table into RAM blocks. RAMs are typically 16x2 or 32x2, depending on the FPGA family.

It shouldn't -- the only difference between a 13-input and 2-input NAND gate is the number of emitters on the input transistor (assuming you're referring to TTL here).

I'm assuming he means that building a 13 input NAND using discreet components with less inputs would add gate delays.

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@loop: lda (src),y — sta (dst),y — iny — bne @loop — inc src+1 — inc dst+1 — dex — bne @loop