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GARTHWILSON
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PostPosted: Tue Oct 12, 2010 1:23 am 
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Okay, details man! Details!
NS access times? Cost?

I'm in the process of designing it.  The initial one is planned for holding 8 512Kx8 10ns SRAMs, which currently are at a little under $10 per chip [but see the edit below], and I probably won't initially be able to buy enough at a time to get any significant discount.  So my cost on just the chips will probably be around $70 per set of 8.  I haven't figured out yet how the tool-up cost of boards will amortize out.  The cost for each bare PC board is rather trivial, but the PCB manufacturing set-up charges are not, so the quantity will dramatically affect the per-piece price.  Then I'll have to factor in the assembly labor.  The other parts' cost is piddly.  I've done enough investigating to know that it's feasible, but it will be awhile before I can sharpen my pencil and come up with a final price.  After this first one, I hope to make other densities of SRAM modules and other types of modules.

Edit: I came across this again five years later, and realized I never edited it to give the info.  The module is shown on the front page of my website (linked at the bottom of this post), and the data sheet is at http://wilsonminesco.com/WM-1_4Mx8SRAMmodule4-23-20.pdf .  I wrote above that the ICs were nearly $10 each.  I'm getting them now, in quantity, at $2.50/each, probably far less than you can get them in small quantities, then there's the PCB itself, connector, and capacitors, and I am letting the parts go for my cost and adding about $40 for my labor (if the module is fully populated) to assemble and test each module.  The price on the ICs is different every time I order though.  (Hopefully now it will only go down, but that has not always been the case.)  As of Jan 2017, I'm asking $69 for each fully populated module.  Lesser populated ones (ie, having less than 8 SRAM ICs on it) cost somewhat less. [end_edit]

A discussion of the consortium plan is material for another forum topic, but here's a taste.  Daryl is in on this informal "consortium" too, and others are welcome.  The idea of the consortium is to have various members who, although not obligated to each other in any way (eg, they are not business partners together nor are they bound by contract) agree on simple technical standards (like 65SIB) for the benefit of all, and cooperate to offer different compatible modules and other hardware, to make 6502 construction and use easier and more rewarding for hobbyists and possibly schools and anyone else interested.  I've been wanting to do this for years, but now my job situation makes me think I should get something going on the side, which is an added excuse and motivation.

There was a cartoon published over 100 years ago.  Two neighbors are talking, and one says to the other, "I hear you've gotten yourself an automobile.  Why haven't I seen you out in it?" and the other, both proud and embarrassed, says, "Oh, I'm still learning to make my own repairs."  With no history of automobiles to go on yet, the buyer who received his prize possession in a crate "with some assembly required" had to figure out how to get it going (with no support) and then how to do the regularly required repairs, or it was of no use to him.  That's kind of how the 6502 hobby world has been.  If the consortium goes as I imagine it, the 6502 world should be gaining a lot of momentum.

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digidice
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PostPosted: Tue Oct 12, 2010 5:45 am 
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The consortium sounds like a good idea, the premise of making modular components that hook together like an erector set would be really nice, Is there any docs about how the hardware parts should be connected for a standard?
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GARTHWILSON
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PostPosted: Tue Oct 12, 2010 8:08 am 
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Is there any docs about how the hardware parts should be connected for a standard?

Since the consortium has just started to form, there's nothing to offer yet except that before the consortium idea was born, we developed the 65SIB spec here on the forum.

One other very simple specification I anticipate will be presenting and finalizing soon is a hobbyist-friendly I²C connection standard for sharing tiny I²C hot-pluggable plug-in modules.  [Edit: It's at viewtopic.php?f=4&t=2155 .]  We're definitely not trying to hide anything but just have been too busy to bring it up for comment.  It's basically the same as I've used for the half-postage-stamp-sized serial EEPROM modules I've posted pictures of but there's an additional pin for IRQ\ (like for real-time-clock alarm output) and a keyed connector to keep one from plugging it in backwards.  I would be very surprised if there's any disagreement to iron out, because it's just so simple.  There was a little company in, IIRC, Australia that tried to establish a standard connector for I²C modules; but theirs was not commonly available, nor did it fit into standard perfboard we hobbyists use with ten holes per inch.  [Edit: Now we also have the hobbyist-friendly SPI-10 connector standard for tiny SPI flash and other modules.]

I believe another member is devising a low-pin-count (maybe 16?) parallel expansion bus for custom I/O peripherals like making your own video card, implemented using low-cost microcontrollers but which appear to hang directly off the CPU bus even though they don't load it significantly or slow it down like other buses do.  Four-phase transfers allow peripherals to run at their own maximum speed without the computer having to know what that is.  The low pin count makes construction easier, and the ATmega or PIC microcontrollers are quite a bit cheaper than CPLDs and easier to program at home.  They should be made available pre-programmed for those who aren't into programming their own.  This is not a competitor to 65SIB.  They meet different needs.

Then of course will be actual hardware we hope to make available.  Your "erector set" analogy kind of gives the idea, and Wally Daniels has used the term "Legos," but it would be nice to find a term that relates more to the fact that 's more specific to the completed modules made available.

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kc5tja
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PostPosted: Tue Oct 12, 2010 4:28 pm 
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GARTHWILSON wrote:
I presented the idea of a 32-bit 6502 in hopes of attracting the programmable-logic designers, something I did not succeed in.


I'd like to try my hand at Verilog after the end of this year. I think I will tackle this design. Contact me again if I forget, please.
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kc5tja
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PostPosted: Tue Oct 12, 2010 4:33 pm 
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digidice wrote:
Backwards compatibility has been the bane of x86 tech for nearly 20 years now.


It's also what ensured its market success.
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digidice
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PostPosted: Tue Oct 12, 2010 5:50 pm 
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kc5tja wrote:
digidice wrote:
Backwards compatibility has been the bane of x86 tech for nearly 20 years now.


It's also what ensured its market success.


Thats not exactly true, It may have been part of the factor, but overall machine expense was the number one reason, You could buy 3 or 4 PC's for the price of a Mac.
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BigEd
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PostPosted: Tue Oct 12, 2010 5:57 pm 
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GARTHWILSON wrote:
...One thing that does bring to mind however is that even at reset, the processor does immediately write to the stack in page 1 (since it comes up in emulation mode), before even the first instruction of the reset routine is fetched...

Hi Garth
are you sure about this? It looks like the nMOS 6502 doesn't do this - indeed it seems like a bad idea because reset writing to the stack is a destructive thing to do. (Even if reset was used as a warm reset, one wouldn't normally worry about preserving the stack content, but even so... maybe page 1 has something important mapped in, even peripherals, or the famous 128 bytes mapped into both pages 0 and 1.)
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GARTHWILSON
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PostPosted: Tue Oct 12, 2010 6:36 pm 
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Ed, I haven't tried it on an NMOS one, but I have with CMOS, single-cycling and seeing what's on the buses at each phase-2-high time.  This was before I saw the same info in the cycle-by-cycle info in WDC's data sheet.  It does indeed push the address and status on the stack, which might be a good thing if you wanted to see which way the bear went into the woods that required the reset to get control back.  I've never done that though.  RST is basically an interrupt, although I never thought of using it that way.  Hmmm... maybe there's another hidden use there.

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BigEd
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PostPosted: Tue Oct 12, 2010 6:53 pm 
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Hi Garth
Michael Steil says that the normal interrupt sequence is followed - there are three stack accesses - but that RnW stays high, so there are no writes.
Do you believe you saw writes, or did you just see the addresses?
(I'm interested in this because I want to trace the part of the design which adjusts RnW.)
Cheers
Ed
ps. I'm not sure yet I agree with his statement "When a 6502 is turned on, the stack pointer is initialized with zero." but I haven't yet run this case through visual6502.
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GARTHWILSON
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PostPosted: Tue Oct 12, 2010 7:32 pm 
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Michael Steil says that the normal interrupt sequence is followed - there are three stack accesses - but that RnW stays high, so there are no writes.
Do you believe you saw writes, or did you just see the addresses?

I'm sure I saw writes (ie, R/W\ was low) but I'd have to dig it up to be more than 90% sure.  The WDC manual also says they are writes, with R/W\ low.

Quote:
ps. I'm not sure yet I agree with his statement "When a 6502 is turned on, the stack pointer is initialized with zero."

In school in 1982 we were taught to always initialize it in the reset routine.  That was on the NMOS 6502 but what I find in WDC's data sheet is "All Registers are initialized by software except the Decimal and Interrupt disable mode select bits of the Processor Status Register (P) [which] are initialized by hardware." (page 11).  IOW, your reset routine has to initialize all but the D and I flags.

If you leave the entire page 1 of a 6502 for the stack, it wouldn't really matter if you initialize it, because there won't be anything to overwrite; but my own tests have shown that I don't need anywhere near that much stack space even with heavy use of subroutines and interrupts; so I use some of page 1 for variables and of course the stack must be kept in its place to avoid stepping on them.  [Edit, years later: There is another good reason to initialize the stack pointer, which is to make sure you don't accidentally index into page 2 if the stack wraps.  More on this in my stacks treatise, starting in the middle of page 4 on stack addressing, at http://wilsonminesco.com/stacks/stackaddressing.html .]

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BigEd
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PostPosted: Tue Oct 12, 2010 7:39 pm 
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Thanks for that - it sounds like WDC added some initialisation hardware and subtracted a bit of reset-being-non-destructive hardware!

Cheers
Ed
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GARTHWILSON
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PostPosted: Tue Oct 12, 2010 8:20 pm 
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BTW, when I did my single-cycling test mentioned above, that was on a Rockwell 65c02, not WDC, but it agreed with WDC's data sheet.

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HiassofT
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PostPosted: Tue Oct 12, 2010 9:56 pm 
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GARTHWILSON wrote:
I'm sure I saw writes (ie, R/W\ was low) but I'd have to dig it up to be more than 90% sure. The WDC manual also says they are writes, with R/W\ low.

Very interesting, thanks for the info!

After Michael's blog post I was very interested about seeing this in action so I hooked up my logic analyzer to my Atari 800XL and captured some traces.

Unfortunately Antic dram refreshes destroy the nice pics, just ignore all cycles where HALT is low (in the pics I shifted halt by 400ns so that it's in sync with the stopped clock cycles). To make the actual CPU cycles easier to recognize I set a marker at the start of each CPU cycle.

Here's the powerup:
Image


And here's the reset:
Image

I hope that I'm able to capture traces of the 65C02 in a few weeks, a friend was so kind to send me a few 65C02s, now I only need the adapter board.

so long,

Hias
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BigDumbDinosaur
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PostPosted: Wed Oct 13, 2010 4:23 am 
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digidice wrote:
there is a 74F138 but no 74ABT138

Correct on that. Not all parts will be available in all logic families. That was why I suggested ABT, F, AC.

Quote:
#5 A AND gate from /Ø2 and RWB to the /WE on the SRAM? That should qualify?

Naw, your logic will be upside down. Connect Ø2 to one input of a 74ABT00 NAND. Connect RWB to an inverter (74ABT04, for example) and connect the inverter's output to the other input of the 74ABT00. The 'ABT00 output will go low when Ø2 is high and RWB is low. The slight prop delay of the inverter won't matter because RWB will be low before Ø2 goes high.

Quote:
#6 You say Potato, I say Potàto. :) I can put GND signals in there it it makes it easier for everyone.

It's your design, so use what makes you happy. I just avoid designations that sound too much alike, as it's only a matter of time before one gets confused with another and the smoke generator starts up.

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BigDumbDinosaur
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PostPosted: Wed Oct 13, 2010 4:36 am 
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GARTHWILSON wrote:
Quote:
Okay, details man! Details!
NS access times? Cost?


I'm in the process of designing it. The initial one is planned for holding 8 512Kx8 10ns SRAMs, which currently are at a little under $10 per chip, and I probably won't initially be able to buy enough at a time to get any significant discount. So my cost on just the chips will probably be around $70 per set of 8. I haven't figured out yet how the tool-up cost of boards will amortize out. The cost for each bare PC board is rather trivial, but the PCB manufacturing set-up charges are not, so the quantity will dramatically affect the per-piece price. Then I'll have to factor in the assembly labor. The other parts' cost is piddly. I've done enough investigating to know that it's feasible, but it will be awhile before I can sharpen my pencil and come up with a final price. After this first one, I hope to make other densities of SRAM modules and other types of modules.

How about something like this?

Image

The above is on a two-layer board and accepts 512K x 8 SRAM in SOJ32 packaging. I also have a 4-layer design that is very similar. In both cases, the SIMM fits into the same card-edge receptacle that accepts 32 bit PCI cards. Four of these would fully populate an '816 system with 16 MB of static RAM.

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