Thanks for your comments. Some things I've already thought about, see my comments.
BigDumbDinosaur wrote:
A couple of things come to mind, in no particular order:
1 ) Defective 512k SRAM.
I've tested two different RAM chips, both of the same type though. I ordered a (hopefully different type) replacement, which already is in the mail.
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2 ) Temperature rise, which could explain why the circuit runs for a relatively long time before errors start. Try cooling the SRAM when the circuit starts acting up.
IIRC one of the original tests were with an improvised heater - a 100W light bulb close to the boards lighting them, but I'll probably do them again. Nevertheless, the boards have no case, and after an hour (or even 30min) I'd expect the board to reach a steady state)
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3 ) Attempting to read/write the SRAM before Ø2 goes high.
/CS is gated with phi2
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4 ) Some kind of decoding error that occurs only with certain addresses.
The MMU I use in the CPU board is set such that all A16-A18 are low. I've also replaced the MMU in some tests, but no change.
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5 ) Not asserting /CS as soon as A0-A15 become valid. It's possible that if /CS isn't asserted until Ø2 goes high, the SRAM may not be "opening" D0-D7 until late in the bus cycle.
6 ) Asserting /WE or /OE before /CS. Most literature I've read implies that it's never safe to assume that a chip will correctly behave if /WE and/or /OE are low before /CS is brought low.
That is interesting. In my understanding the RAM internal control logically "and" the CS, OE and WE lines appropriately so it does not matter which one is first. The 32k RAM chips never cared. In the board I have in fact gated /CS with phi2, and only now also gated /WE with phi2. I'll try to change that to directly use /CS (and possibly gate /OE with phi2) instead.
How does your comment 5) here actually go together with 3)? When Ax become valid, it's some time before phi2 goes high actually.
Do you have any links to the literature you mention?
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7 ) Lazy control signal transitions due to capacitive loading.
Normally I'd say no problem with 1MHz or even 2MHz, but signal edges have much higher frequencies in them, esp. with faster logic chips.
What makes me wonder, though, that the 32k RAM chip uses the same control signals and works.
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8 ) "Dirty" Ø2 waveform. CMOS version of the MPU are somewhat fussy about Ø2 rise/fall time.
9 ) Crosstalk between board layers.
Could very well be the case, although, again, the (slower!) 32k RAM chip works.
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10 ) Too much prop delay in the glue logic.
The same symptoms appear in 1MHz and 2MHz, so if it's that it could only be on the falling edge of phi2 - but again, the 32k RAM works.
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Perhaps it's time for you to invest in a new(er) 'scope to help you solve this mystery. :D
It's on my wishlist (actually for some time now) but the qualitative results I still get with it have helped me enough so far. In winter it's also a nice additional heating - only in summer it's too hot to use ;-)
Currently an older CPU board with all drivers (even data bus) being 74HCT245 is running for over an hour without fault. I'll still have to check though if this board also produces the error when I use (A)LS type ICs instead.
André