Hi there,

I've finally made my 65816 replacement card for the 6502.

Runs up to 12.5MHz, CPU clock asynchronous to the system (6502) clock, synchronized by a CPLD. All 5V and through-hole technology.
Includes up to 1MHz fast RAM (at CPU speed) and up to 512k in-system programmable Flash ROM.

http://www.6502.org/users/andre/cbmhw/pet816/index.html

Board schematics, as well as VHDL code available on the site.

First page rushed out in time for the VCF PET alive event. More specs, docs and explanations to follow.

Have fun.
André

Congrats! A turbocharger, I like.

GTKwave looks nice, I'm gonna get me one.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Excellent - well done! You got yours done before we finished debugging ours.

Actually it is not yet finished too. It runs stable at 8.3MHz - but further tests yesterday showed errors at 12.5 MHz. Not sure if I manage to get that ironed out with a 15ns CPLD and 55ns RAMs though. Over the weekend I want to make the clock divider not use 25MHz but 50MHz as input, so I can get to clock speeds between 12.5 (25/2) and 8.3 (25/3)...

André

Ah and of course I am looking into more features. write-through video RAM for example. Write would be slow (through to the original system) but reads would read from the fast RAM :-)

Yesterday I managed to pull the 74ALS573 functionality into the CPLD as well - but the CPLD is almost full now. So I'll probably keep the 74ALS573 and use the CPLD space for more experimentation (see above). And with the current schematics, pulling the '573 is done by just pulling the chip from the socket and reprogramming the CPLD (e.g. make A16-A18 outputs instead of inputs), without any soldering involved, so I'll keep it in the final board design.

André

Hallo André,
[quote="fachat]... so I'll keep it in the final board design.[/quote]
I would be interested in a bare board, including a CPLD. If possible at all of course. And I think others may be interested as well. It is a way to cover your costs.
Herzlichen Dank im voraus!

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André,
couple of compatibility questions for you: does the PET have a constant clock speed or does it slow down for peripherals? And, have you tried your board in any other types of machine, and do you intend to? (Ours didn't work very well in an Oric)

The PET has a constant clock speed of 1MHZ. I intend to test it also with my selfbuilt 6502 with 2MHz.

The falling edge of the 6502 phi0 input is used to synchronize with the main board. The 65816 fast clock is asynchronous with it. I have yet to calculate the timing values to determine the maximum main board (6502) clock speed.

More details:

A slow access is detected when the fast clock goes high and the relevant address values are detected.

The 6502 falling edge clock signal is delayed by some 50MHz cycles, then it is checked whether a slow access is required by the 65816. If it is so, then the slow access is initiated. If the slow clock is fast enough that the mentioned delay does not leave enough address setup time until the 6502 clock goes high again, the problems start - but could probably be fixed by reprogramming the CPLD to use a shorter delay.

Also there is some teardown time, when the slow access has been finished. The fast clock is stopped during a slow access, and is restarted only a short time after the falling edge of the slow clock.

Due to these delays, the fast clock must be between approx. 2.5MHz and 3MHz, to actually let the CPU run in slow memory with effective 1MHz. A delay after each slow access, then a fast phi0 low half-cycle until the next slow access is detected, then hoping that the address setup time for the slow memory is still ok, all this adds up.

When the CPU does not access the fast memory, it clears the slow address bus to a read access on address $0000. That was the last change I did, using 74ALS273 registers instead of normal drivers. The problem is that there is no "address is valid" line on the 6502 bus, and the naive idea of tri-stating the drivers plus pull-ups wasn't stable enough.

You can have a look at the schematics and the VHDL from the web site. you might be interested in the generation of the cpuclkint signal, which is the fast clock and the ClockSync component. If you have any questions, just ask (also by PM)

André

Thanks for the extra info. I'll have a good look at your sources!

I think you have an advantage there in designing with a fast enough master clock that you can take clock switching decisions synchronously. Nice.

The write-through to slow memory is a win - we did that too. I think we have an option for mapping the non-video RAM at full speed, and for mirroring ROM. If we could spare the gates for the address decode, we only needed host accesses for peripherals.

Cheers
Ed

Don't look to hard, they are not really cleaned up :-)


I used a 50MHz clock oscillator on the 65816 board, so I could delay signals in a very fine manner, 20ns per clock cycle, or even 10ns if I use both edges.

It also allows me to fine-tune the 65816 clock by setting the clock divider to an appropriate value.


The main mode of operation for the board as planned is to copy the ROM to fast RAM - I even have a write protect option for bank0 from $Axxx or $Cxxx or $Exxx up to $FFFF - and then completely run in fast memory.
But writes to the slow memory in bank0 are always written through to the fast memory too. So it would be possible to just copy over the ROM and then switch to fast mode.

I only ran into one problem with the CBM8296 - which itself has a write-only memory configuration register at $FFF0. If you write to that during the copy operation, the memory config changes and if you don't care for that it doesn't work. For this reason I have mirrored the lowest 512k of fast RAM at $F0xxxx-$F7xxxx (the flash ROM is at $F8xxxx-$FFxxxx) and do the copying into this area.

Only video RAM and I/O are mapped to the original bus/places in bank0. And only for the video RAM I'm planning for a "fast-read" option (as writes are already write-through).

The board has one (one more planned as more options come) write-only registers where you can map bank0 to the original system or to fast RAM, speed up bogus cycles only (the board uses VPA/VDA), to set the clock divider, disable flash ROM write protect etc.

André

you can also have a look at the GTKWave screenshot on the site with the simulated timing diagrams. This should help you find your way around the different signal timings.

IIRC I put up the place where a write to the configuration register takes place ($EFFF) where also the speed is changed to a faster values, which makes the clock pulses shorter

André

Just an update. I am working on a 2MHz system for a test setup. I.e. a 2MHz base system with the 65816 card in it. Unfortunately the benchmark I've been writing runs on a Commodore PET, so I have to fixup the PET's IEEE488 interface which is failing at higher speeds. That's where I'm stuck at the moment.

OTOH, I earned an "award" for the "Most genetically-enhanced PET" from the Vintage computer forum's "PET alive" event :-)
http://www.vintage-computer.com/vcforum ... ent-Thread!

André

Edit: the URL thing does not seem to work with this particular URL

That's a good result, congratulations!

(You should be OK with the URL thing if you replace the ! with %21 codes, like this)

Another update..

I was testing the board in a 2MHz host system, and found some problems - but now I found that these problems most likely were problems of the host system already! (kind of embarrassing though, as I designed the host as well...)

So I'm postponing this (assuming that if I can recreate the problems of the original system, the board must be pretty ok anyway :-) and continue with the next prototype version, and CPLD software version.

André

Another update - now that I fixed the problems with my 2MHz test system, I managed to fix the VHDL such that if you put the 65816 board in a 2MHz system (or slower) it should run (in the startup configuration) at original speed.

I originally thought that not to be that important, but then I experienced with c2n232 on my test PET, with the card installed and it wasn't working...

I hope I get some updates ready for my website the next weekend

André