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 Post subject: 6502 in FPGA
PostPosted: Thu Oct 08, 2009 8:37 am 
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Hallo allemaal,


Please have a look at this: http://www.baltissen.org/images/gideon2.jpg

If you don't recognize it, this is FPGA replacing the 6510 of a Commodore 64. My question: is it possible for someone on this list to design, build and, most important, to sell a small board that contains:
- FPGA, EEPROM and other needed hardware needed to make the FPGA work at all
- 40 pin header so the board can replace a 6510
- (JTAG ?) connector to be able to reprogram the EEPROM/FPGA
- "left over pins" header.

The basic idea is that, when correctly programmed, this board should at least be able to replace any 6502 or 65C02 (maybe even a 65816). With a working base, anyone can add new/replace instructions at their own will.
The "left over pins" header is for people who want to expand their system with extra data lines, address lines, CE lines or whatever comes to their mind.

I hope anyone can take up this idea!


Update: Have a look at http://forum.6502.org/viewtopic.php?t=1673&postdays=0&postorder=asc&start=0 please!

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Last edited by Ruud on Mon Nov 01, 2010 10:44 am, edited 1 time in total.

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PostPosted: Thu Oct 08, 2009 9:27 am 
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Your wish has come true.

Enterpoint in the UK already sells exactly what you're looking for: FPGA modules in 40pin DIL boards as plug-in replacments for obsolete components.

http://www.enterpoint.co.uk/component_r ... gnell.html

There's an example of this module being used as an 8088 replacement here:

http://www.ht-lab.com/freecores/cpu8086/cpu86.html


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 Post subject: also by OHO at Trenz
PostPosted: Thu Oct 08, 2009 10:51 am 
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OHO Elektronik do something similar, sold through Trenz Electronic in Germany, although it isn't easy to find on either site.

I think in both cases the choice of VDD and GND pin is configurable but not totally free - with luck the right pins are valid choices. (*)

See
http://shop.trenz-electronic.de/catalog ... cts_id=634
(GODIL40_XC3S250E DIL FPGA module 40 pin DIL TE0261-00, )

(*) Edit: in fact, the power supply pins on the GODIL are freely configurable.


Last edited by BigEd on Sat Apr 10, 2010 7:23 pm, edited 2 times in total.

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PostPosted: Thu Oct 08, 2009 10:52 am 
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thargoid wrote:
Your wish has come true.

Unfortunately not. The replacement board only provides 38 programmable pins. That's OK if you only want to replace the 6502, but if you want some extra address lines or what ever.....

But thanks anyway for the link!

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PostPosted: Thu Oct 08, 2009 12:02 pm 
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If you need access to more than 40pins, OHO do 48-pin DIL and 50-pin IDC versions, and in all models there are 7 more I/Os available for expansion.

http://shop.trenz-electronic.de/catalog ... cts_id=632

http://shop.trenz-electronic.de/catalog ... lter_id=18

The documentation looks good: GODIL User Manual at http://www.trenz-electronic.de/support/ ... dules.html


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PostPosted: Fri Oct 09, 2009 3:09 pm 
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Ruud wrote:
... only provides 38 programmable pins. That's OK if you only want to replace the 6502, but if you want some extra address lines or what ever...

Just a thought: you could use the 65816 trick of multiplexing using the clock phases. The data bus and possibly the i/o ports could serve double-duty, for the cost of an external latch. (I don't know if C64 or C128 timings would let you get away with this)

I like the overall idea though! I'm looking into three ways of doing something similar: plug-in upgrade, TUBE-connected, and single board computer. I'm hoping to find a way to design a board which can serve two or maybe even three of those purposes - once you've got reconfigurable logic, flexibility should be in reach. Having jumpers and optionally populated sockets should help too. Right now the OHO approach looks attractive to me.

I'm using the free version of Eagle PCB, which is for non-commercial use, so no help to you, unfortunately.

(TUBE being the coprocessor interface for the BBC micro)


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PostPosted: Sun Oct 11, 2009 8:32 pm 
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BigEd wrote:
(I don't know if C64 or C128 timings would let you get away with this)


They would not. The VIC-II chip uses the bus during phase-1, even when the display enable bit is negated, since the VIC-II handles DRAM refresh.

Thus, you'll need to isolate the CPU from the rest of the C64 with external three-state buffers if you wish to multiplex I/O on the data or address buses.


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 Post subject: Re: 6502 in FPGA
PostPosted: Mon Oct 12, 2009 11:21 am 
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Hi Ruud

I have lots of questions!

Ruud wrote:
Please have a look at this: http://www.baltissen.org/images/gideon2.jpg

If you don't recognize it, this is FPGA replacing the 6510 of a Commodore 64.


So, what FPGA is this? Is there a freely available 6510 source for it? Do you own this design? And, most importantly, in what way is this design not the same as the one you're looking for?

Is it easier to make a 5v compatible device with Altera than it is with Xilinx?


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 Post subject: Re: 6502 in FPGA
PostPosted: Tue Oct 13, 2009 10:13 am 
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BigEd wrote:
I have lots of questions! ....

This is a PCB made by and belonging to Gideon Zweijtzer, creator of the 1541Ultimate. So I cannot answer any of the questions by lack of knowledge. If I owned it, there was no need to place the original message....

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PostPosted: Tue Oct 13, 2009 9:04 pm 
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Ah, thanks - all is explained.

That product of Gideon's is quite complex. I like the way one of these DIP-based boards would handle a lot of that complexity (and some SMD difficulty)

I see Enterpoint do a 40pin module which also includes 256Mbit of RAM:
http://www.enterpoint.co.uk/component_r ... nell2.html There's no additional i/o for storage or other expansion, but it looks like they would, for quantity, offer some flexibility - up to 68 pins.


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PostPosted: Fri Nov 06, 2009 10:19 am 
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kc5tja wrote:
The VIC-II chip uses the bus during phase-1, even when the display enable bit is negated, since the VIC-II handles DRAM refresh.

Thus, you'll need to isolate the CPU from the rest of the C64 with external three-state buffers if you wish to multiplex I/O on the data or address buses.


Hmm, the C64 looks like a difficult case: both the cartridge port and the CPU socket are at best co-processors. (I'm familiar with the BBC micro, where the CPU is in charge, at least during phi2).

So yes, looks like bus isolation is needed. Perhaps an 84-pin CPLD would do nicely to isolate a private bus from the host? Then the FPGA CPU doesn't have to be pin-compatible with 6510.

I see Ruud has previously tackled a C64 cartridge coprocessor.

And Gideon has a good description of the difficulties of being a C64 coprocessor.


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PostPosted: Fri Jan 15, 2010 2:12 am 
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VHDL is the key. Still looking for a free 6502 VHDL core... One to understand from, not to just copy, I'm sure they have bugs anyway. When I was younger, 6502 assembly was my obsession, just because of the awesome speed difference compared to Basic on the C64, which was my first language. It is a logical step to learn VHDL to emulate a 6502 in VHDL to run in an FPGA many times faster than the 6502's found on the market today. Speed is still THE issue, mod's are a close second.

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PostPosted: Fri Jan 15, 2010 4:15 am 
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ElEctric_EyE wrote:
Still looking for a free 6502 VHDL core...


The T65 core and derivatives are VHDL. From a previous post: "The T65 has suffered from a re-org at opencores, but can now be found here - but I think there have been subsequent fixes so check also at https://svn.pacedev.net/repos/pace/sw/s ... onent/cpu/ (*) and http://www.fpgaarcade.com/library.htm "

See also Sprow's Free6502 page which has the original and his modified versions.

(*) site has bad https certificate, but the archives are there.

(*) the pacedev archive version fixes a problem with the B flag


Last edited by BigEd on Mon Mar 22, 2010 1:11 pm, edited 1 time in total.

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PostPosted: Fri Jan 15, 2010 4:23 am 
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http://web.archive.org/web/200406032220 ... index.html
It took quite awhile to load, but it did eventually come, so be patient.


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PostPosted: Fri Jan 15, 2010 5:13 am 
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From my experience at Hifn, I'm a fan of Verilog -- VHDL seems much too verbose for what it's trying to accomplish. Being a proper subset of Ada, expressing certain concepts is awkward for me. Verilog seems more purpose-built to the task of hardware synthesis and simulation.


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