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PostPosted: Wed Jan 13, 2010 6:26 pm 
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Are there any documents which corroborate this? I've not seen anything online yet which supports this.


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PostPosted: Wed Jan 13, 2010 8:48 pm 
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Low voltage, low power VLSI subsystems By Kiat Seng Yeo, Kaushik Roy, ISBN-10 007143786X..


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PostPosted: Wed Jan 13, 2010 10:10 pm 
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OK, but, while you might need more gates for equivalent asynchronous logic, you also don't have clock distribution and skew processing logic either. So, at what point do the power-versus-logic-complexity graphs meet? That's what I'm interested in. This book doesn't address that issue at all.


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PostPosted: Thu Jan 14, 2010 12:22 am 
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OwenS wrote:
kc5tja wrote:
(2) The conclusion exposes the author's complete misunderstanding of the purpose for using asynchronous logic. Even if you use an asynchronous CPU in an otherwise synchronous environment, you get the benefit of a chip which draws significantly less power (if implemented correctly; I'm not sure this would work in an FPGA environment), is much quieter in terms of RF hash, and which produces substantially less heat. These all can be extremely valuable qualities. For example, on an Intellasys SEAforth 24A chip that I have, I had all 24 cores running full blast at an estimated 650 MIPS each, and that chip only became two degrees warmer. ONLY two degrees! And, if my ham rig is any indication, it had no observable hash emissions; everything it put out was well below nature's own noise floor. Contrast this against my desktop PC, whose emissions are so strong I can hear it in my headphones when the sound card is silent.


With desktop class IC processes, an asynchronous processor consumes far more power than a synchronous one. Why? Because leakage current is higher than switching current. Modern processors use FETs with threshhold voltages of 200mV, and 1V power supplies. Therefore, power consumption is linear with powered transistors; clock frequency is not a major factor. Asynchronous designs, as we have established, use more transistors.
...


Heres another data point.

I'm currently working in the VLSI group of a microprocessor company. From what I've heard, over half of our power budget is used by leakage current. So clock gating doesn't seem to help very much.

Toshi


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PostPosted: Thu Jan 14, 2010 2:57 am 
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Good chart here on page 16:

http://www.upcrc.illinois.edu/summer/sl ... o_Snir.pdf

You can see the passive power as a percentage of total power used, and it's roughly about half with current technology.

Toshi


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PostPosted: Fri Jan 15, 2010 4:02 am 
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BitWise wrote:
kc5tja wrote:
Xess sells a Xilinx Spartan 3-based development board, with what appears to be a one million gate FPGA, for $199:

http://www.xess.com/prods/prod035.php

I was thinking about acquiring one of these boards to play with some time ago. 1 million gates is a lot of gates to have fun with. :)


Yep. Its a nice bit of kit. I bought one a few years back.


Nice! At $200 and about 4 or 5 times the capacity of one of those DIP modules, it looks like slightly better cost per gate. The 16-bit channel to SDRAM is attractive!

kc5tja wrote:
1 million gates is a lot of gates to have fun with. :)


Back in August I did a quick mapping of Rob Finch's 6502 core into a 250k-gate device, and it came out at 18% utilisation. So 250k looks like plenty for me at present.


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PostPosted: Sat Jan 16, 2010 2:06 am 
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BigEd wrote:
...Back in August I did a quick mapping of Rob Finch's 6502 core into a 250k-gate device, and it came out at 18% utilisation...


Were you able to successfully program the FPGA (i.e. use it as a plug-in substitute)?... Or was it all software sim?

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PostPosted: Sat Jan 16, 2010 9:55 am 
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ElEctric_EyE wrote:
BigEd wrote:
...Back in August I did a quick mapping of Rob Finch's 6502 core into a 250k-gate device, and it came out at 18% utilisation...


Were you able to successfully program the FPGA (i.e. use it as a plug-in substitute)?... Or was it all software sim?


At that time I didn't have an FPGA to program! I hadn't taken any care about pin assignments either - I would expect that I wasn't very far from having a plug-in substitute, but that's theory rather than practice.

Now we do have an FPGA to program, but we're trying to concentrate on the 816-in-beeb project. Distraction is the enemy! I would hope that some time this year we'll be doing interesting things on FPGA, and a straightforward 6502 plug-in sounds like a good learning exercise. (A 6510 plug-in is a simple next step beyond that: I have a C64 but I expect the CPU isn't socketed, so there's a little barrier there.)


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PostPosted: Mon Jan 18, 2010 12:55 am 
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kc5tja wrote:
Xess sells a Xilinx Spartan 3-based development board, with what appears to be a one million gate FPGA, for $199:

http://www.xess.com/prods/prod035.php

I was thinking about acquiring one of these boards to play with some time ago. 1 million gates is a lot of gates to have fun with. :)


This looks like a great prototyping tool to learn VHDL. It's using the Xylinx XC3S1000-4FT256, according to the bottom of pg.39 ( http://www.xess.com/manuals/xsa-3S-manual-v1_1.pdf ). The identifier in bold clues you in to how many I/O pins it has, thereby changing how many pins overall...
I would hate to spend alot of time programming a prototype only to find the FPGA is out of production, so I searched for the individual FPGA from my favorite supplier. They have 700+ of 'em, for ~$50 each: http://search.digikey.com/scripts/DkSea ... k=xc3s1000

researching BGA socket adapters...

1 question thought to those wwho may be in the know: The XC3S1000 series doesn't need the supporting SRAM and other IC's on the Dev board in order to work does it?

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PostPosted: Mon Jan 18, 2010 4:18 am 
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I once owned the 200 board - very similar. While I never used it, I did read quite bit. As I recall, the only thing an FPGA will require is the ROM device that holds its programming.

On these dev boards, they add things like SRAM, VGA, and other parts to allow for experimenting. The XC9572 is used as glue logic to allow for connection to the host PC during development. It can program the ROM, communicate with the FPGA, or do other duties.

My board also had a programmable TTL oscillator 100MHz max divided down to whatever speed you wanted. The XC9572 could be reconfigured to allow for programming of that device also. IIRC, the newer board has a fixed oscillator and you would have to built a divider inside the FPGA.

Hope that helps...

Daryl


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PostPosted: Mon Jan 18, 2010 8:53 am 
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On the Xess board the Flash RAM is used to hold the FPGA configuration. You can simulate small RAM and ROM areas within the FPGA. The DRAM is provided for projects that need larger memory areas, say for VGA generation.

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