Ruud wrote:
Nightmaretony wrote:
http://www.6502.org/users/dieter/m02/m02.htm
Thanks for the URL, lost it some time ago.
But with all respect, this is what I call a simulator, not an emulator. Not having PHI2 (as the site states), I wonder how it can replace a real 6502.
My goal is a CPU that can replace a real CPU using PHI0 as timing.
My design is not using micro-code AFAIK. The AT29C040's I intend to use should mimic the instruction decoder of the real 6502.
But now a for me a bit embarrasing question: how does this micro-code stuff works? I always thought that I had to see it as a mini CPU using only a few basic opcodes needing some cycles to run the actual opcode. But that doesn't explain the few parts Dieter need for his CPU(compared to my design). So if anybody is willing give me more details, I would be very thankfull!
Microcode is basically defined by the use of a ROM (or RAM), rather than hard wired logic, in order to execute the instructions. Depending on the architecture, some of the bits of the instruction may bypass the microcode and some may be used to select the microprogram which is used to execute the instruction.
Microcoding doesn't necessitate multiple cycle execution; that entirely depends upon the processor. What it does do, however, is make it easier to implement complex instructions.
Microcode tends to set the control bits for various internal components rather than actually executing opcodes as such. For example, a microinstruction on a RISC CPU might look like
Code:
[ADD] A(RF1)), B(RF2), C(LF3SX), ALUOP(ADD2), WRREG(RF4), WZ(ALU), WC(ALU), NEXT(Execute)
Which says "Instruction ADD, Set bus A to register selected by instruction field 1, set bus B to register selected by field 2, set bus C to literal in field 2 sign extended, execute an "add2" operation on the ALU, write register specified by field four, update the zero and carry bits based upon the ALU's output, and then go to the Execute special vector"
Some vectors, like the aforementioned Execute vector, may be special and recognized by the surrounding logic. For example, Execute might be detected and replaced (Before it reaches the microprogram address) with a value based upon the opcode of the instruction.
As microinstructions can get very wide and have lots of fields, microassemblers tend to have lots of defaults which cause the unmentioned functionality to be fed NOPs (or other sane defaults, which may in some cases depend upon other fields: For example, you probably don't want to execute the instruction pointer during the intermediate cycles of a multi cycle instruction, but it should default to being updated when jumping to the execute vector)