The die size can be found in
patent 4739475 (if you download the pdf you also see some chip-scale layout.)
The hope, it seems, was that 65816 would be half the size of competing 16-bit micros.
If you like a good story, or want some insight into the transistor-level layout-centric approach taken, have a read of the patent. Here's an illustrative snippet:
"As this approach to layout of the sum-of-minterm region 116B progressed, my foregoing hunch turned out to be correct, and with much less effort than I thought might have been required, I was able to complete the layout of the sum-of-minterm region with much less expenditure of time, and with only approximately 40% less chip area than I thought would have been required if I had not hit upon this approach"
Several of WDM's 'topography' patents read like this- quite unlike other patents I've read.