Thanks for the update.
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Aparrently, other 65c22 have ttl level inputs and this is not so with the Western Design chip.
It's not really the level, but rather that CMOS inputs (like WDC has) don't pull themselves up (or down either, for that matter). The input capacitance (even if only 20pF) of a perfect CMOS input with no leakage will hold the pin at the last driven voltage, which could be Vcc or ground (or anything in between), working kind of like a sample-and-hold circuit. WDC intentionally has a small deviation from that, in that they use a bus-holding circuit at the input. It is not explained well in the data sheet, but appears to keep the last-driven logic state at the input pin so it can't drift through the no-man's land between 0 and 1 by itself. Unlike TTL, WDC's outputs can pull up just as hard as down, and can pull a 220-ohm load up to 4.2V, resulting in 19mA current very solidly in the logic "1" territory. (I found this through experimentation. The data sheet won't tell you.)