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 Post subject: W65c22 problem ?
PostPosted: Thu Apr 16, 2009 2:49 pm 
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Joined: Thu Apr 16, 2009 2:20 pm
Posts: 5
Hello all,
Need help here i'm afraid. I normally use the Rockwell part without any problems at all, but i need to use the wdc parts now in order to attain higher running speeds. I have no problems at all with substituting the w65c02 part into the system, it works fine. But inserting the w65c22 into the system causes a peculiar problem, even though i have removed the pull-up resister on the irq line. The input via a membrane keypad seems to be somewhat erratic, sometimes working on some key-inputs but not on others. Are there any other precautions needed to be taken when using this device instead of an R65c22 ?
Regards, sean.


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PostPosted: Thu Apr 16, 2009 6:33 pm 
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Joined: Fri Aug 30, 2002 1:09 am
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Location: Southern California
I have a note here that Rockwell VIA port pins really do present an LSTTL load in input mode. WDC's do not. Does your design expect that an input line that is not pulled up will automatically go up when something is not pulling it down, as would be the case with a key switch?

With the IRQ\ line, removing the pull-up is not enough if other IRQ sources are also connected to it. In that case you would need diodes or an AND gate to isolate them from each other.


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 Post subject: w65c02 problem
PostPosted: Fri Apr 17, 2009 11:35 am 
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The problem in this instance is due to a lack of pull-up resisters required on the port-B inputs and this information was supplied by Garth Wilson. Aparrently, other 65c22 have ttl level inputs and this is not so with the Western Design chip. Anybody using keypad input between port-A and port-B should be wary of this fact !


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PostPosted: Fri Apr 17, 2009 7:04 pm 
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Joined: Fri Aug 30, 2002 1:09 am
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Thanks for the update.
Quote:
Aparrently, other 65c22 have ttl level inputs and this is not so with the Western Design chip.

It's not really the level, but rather that CMOS inputs (like WDC has) don't pull themselves up (or down either, for that matter). The input capacitance (even if only 20pF) of a perfect CMOS input with no leakage will hold the pin at the last driven voltage, which could be Vcc or ground (or anything in between), working kind of like a sample-and-hold circuit. WDC intentionally has a small deviation from that, in that they use a bus-holding circuit at the input. It is not explained well in the data sheet, but appears to keep the last-driven logic state at the input pin so it can't drift through the no-man's land between 0 and 1 by itself. Unlike TTL, WDC's outputs can pull up just as hard as down, and can pull a 220-ohm load up to 4.2V, resulting in 19mA current very solidly in the logic "1" territory. (I found this through experimentation. The data sheet won't tell you.)


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