Hi all,
I'm an italian student. I'm trying to make a vhdl description of processor 6502 for the electronic computers course. I know there are many free vhdl implementation, but i have to make an rtl view and so i need some info that i haven't find yet on the net.

1. what type of registers are acc, x, y, pc, sp, databuf and addrbuf? I don't want any functional explanation, i need to know if they are latch, edge triggered or master-slave and if they are clocked or not (it seems that in the design of the original processor all are non clocked, but all the vhdl on the net make them clocked)

2. Could someone explain me the right timing for read/write memory access? (i'm not so good in electronic field and the timing diagram on datasheets are quite obscure to me )

3. Could someone explain what are the two phase clock out signals for?

4. Is there a table with the propagation delays for each single component of the 6502?

Because i have to describe the original architecture, i can't follow any suggestions to view subsequent processor like 65c02 or the like!
Thanks in advance to all of you guys,
Fulvio

This is an implementation detail -- since it's an RTL description, the only requirement is that it be synchronized against the chip's clock. How you do this is up to you. Since external logic only sees the effects of clock transitions, it won't matter to external devices either.



During Phi2 low, the CPU puts the address on the A0-A15. During phi2 high, the bus transaction (read or write) is completed. The timing diagrams are your best source for this, and truely, they really are the simplest possible timing diagrams you can get. I would recommend becoming familiar with how to read timing diagrams.



Convenience. Phi1 is used to clock logic that works when the CPU isn't using the bus. Phi2 is used to clock logic that works when the CPU is. Depending on your peripheral hardware, you can get by with just one; you can synthesize Phi1 by just inverting Phi2 and vice versa, provided your peripheral can handle the propegation delay.



Again, these are implementation details -- you decide for your own design.

Thanks a lot kc5tja. I hope i'll do a good job!
Cheers,
Fulvio

Not a problem -- good luck on your project.

Will the results of your efforts be published on the Internet somewhere? I'm sure a few folks here might be interested in the project when it's finished.

Well, i have no problem to publish my project on internet, but maybe it could not be of great interest. By the way, I'll post a message on this forum to publish my work. I've not problem to make so, hope someone enjoy it