GARTHWILSON wrote:
WDC's 65816 data sheet has a table of exactly what's on the buses in every cycle of every instruction, and applies to the '02 as well, using footnotes to separate the various conditions.
Garth is referring to Table 5-7 in the '816 datasheet. But FWIW a less confusing introduction to the topic of cycle-by-cycle operation is Appendix A of the
MOS MCS6500 Family Hardware Manual, simply because it doesn't include umpteen '816-specific footnotes. However, for the 'C02 the WDC doc should be your final authority. The NMOS '02 detailed in Appendix A has some very minor differences compared to the 'C02 (the most notable being that the NMOS '02 takes 5~ for opcode $6C, whereas the 'C02 takes 6).
Rule #1 of cycle-by-cycle operation is, every opcode fetch gets followed by another cycle that reads the byte at PC+1 (or the byte at PC is read again if an interrupt is being recognized). Reading the byte at PC+1 is somewhat of a shot in the dark, given that the opcode is still being decoded while the read occurs. But it's a good guess, because often the opcode will be followed by one or more operand bytes.
GARTHWILSON wrote:
Two-cycle instructions like TAX don't care what's on the data bus in the second cycle.
Yes. Although TAX is only a one-byte instruction, the byte at PC+1 is fetched anyway, then discarded.
Alarm Siren wrote:
On the subject of the instruction stream, you'll also need to deal with the fact that the reset process itself is a pseudo-interrupt which will read (and discard) a certain number of bytes before it gets to reading the reset vector.
Perhaps you can use the VPB pin as a reference, since it'll go low during the fetch of the Reset vector... which occurs
after the hard-to-ascertain number of cycles.
-- Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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