Very nice, Axel! If you're able to run Basic then things are going well,obviously! For a final shakedown do you eventually plan to run Klaus's test suite?

A couple of things caught my attention in the schematic. You seem to have a sixteen-bit Stack Pointer, so what up with that?? Also I was wondering if the chip families are as shown -- HC and LS families, for example.

Will you also publish the number of cycles for the various instructions? I'm curious how the cycle counts compare with those of an actual 6502. Also I don't quite understand your comment in your previous post about a slow shift right implementation.

On page one of this thread you posted a block diagram. I assume this has remained unchanged. But if you ever redrawn the diagram it would be nice to see a little more detail, in the control section especially. Congratulations on a great project!

cheers
Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hello,

Thanks Dr Jefyll. Nice to notice that people are interested in this project. Here is some detailed information behind those I have sent earlier.

Basic runs smoothly. I have executed all kinds of math calculations as a stress test. Like calculating prime numbers up to 6h. I ran Klaus's test suite earlier. It passes except flag tests which are obvious since the TTL 6502 has different SR layout.
All TTL chips are LS family despite on whats on the schematic.
I used 16-bit SP flexibility in mind. Now it seems that std msbasic is being used so this is completely unnecessary. Actually, I also had 24-bit address bus on the first drawings.
Microcode doc attached. You may notice that there are some empty cycles. Those are waiting for optimization and has no functional reason. The implementation of the right shift also gets clarified by looking at the doc.
The current block level design is still the same as on the block diagram sent earlier.

Axel.

Few microcode explanations:

R= /Ready signal state (output of U64-B)
A= Previous Carry state for page boundary calculations (output of U70-B)
C= Carry flag state
Z= Zero flag state
N= Neg flag state
V= Overflow fag state

Axel.

Nicely done Axel! I like the straight forward data path and low chip count. Very nice, and very interesting to see how design choices play out. Thanks for sharing the details.

I assume your microcode generator produces alternate versions in ROM for "conditional" execution (as in "A=0: X <- X + $FF;"), correct?

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C74-6502 Website: https://c74project.com

Hi,

Thanks Drass.



You're correct. All of those conditional lines (like A=0/A=1, Z=0/Z=1) are taken care by microcode generator. I've attached a screenshot what it looks like.

Axel.

Got RS232 PCBs and now the AComputer 1.0 is ready. Here are some fresh photos of the complete set and the RS232 board as well.

Axel.

For the record: max stable clock frequency is 1.7MHz
Microcode flash: W29C020C-90B
RAM: IDT71256L70
ROM: AT28C064B

Very unscientific performance test:
20 K=0
25 DIM M(5)
30 K=K+1
40 A=K^2
45 B=LOG(K)
47 C=SIN(K)
50 IF K<1000 THEN GOTO 30

-> 1.05 min

Axel.