Ain't gonna work...

For some reason, apparently the Atmel 22V10C part has a different programming algorithm than a GAL22V10. Daryl has had the same problem trying to program the Atmel part. Since the G540 programmer I used to program the Atmel EEPROM is not officially endorsed by Atmel to program their PLD's and since the G540's manufacturer recommended using the original GAL22V10's (thanks to both for responding to emails very quickly), I started looking up "qualified" programmers. Cheapest I found was about $350...

In the end, to make a long story short, I happened across the "hack-a-day" sight (I know someone else in here linked to the site before, they are top notch). I Googled a beginner tutorial on CPLD's and they do have a very well written up little blurb for beginners. I chose a Xylinx kit for $50.

http://hackaday.com/2008/12/11/how-to-p ... ices-cpld/

But, I can already see I'm going to have to modify it and remove the surface mount XC95xx chip and put a 44pin PLCC socket in there with a higher speed version. As hackaday pointed out PLCC and/or 5v devices seem to be a dying breed. I was able to pick up a few 10ns versions.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The Lattice brand GAL's program fine in my programmer.

Mouser has 10ns, 24 pin GAL22V10D PDIP's for $5.50

Part # is 842-GAL22V10D10LPN

Daryl

I know I should've started out learning PLD's from the simplest IC's, that was my intent. But I'm going to try my hand at learning Verilog with the software that is coming with the XC9572 eval kit. Even these kits have been discontinued by Digilent, only old stock is selling. How far behind am I!... Looking forward to learning Verilog, and the other tools, and work up to the Spartan 3 series FPGA... After doing some research, Xylinx becomes the obvious choice, just because of their support software.

I also found out by posing a few questions on New Haven Display's forums, that the max frequency for the E (phase 2) signal on my 320x240 TFT display is 10MHz, which explains my top 65C02 speed. So I'd bet money my CPU section can go above this if I had a display that could handle the faster speeds. Their 640x480 8-bit display can go up to 55MHz. Even though it uses a different controller IC, data seems to be written in the same manner, so my software will be compatible. When I get some spare $, this display will be my next purchase. I really want to see if 14MHz is a conservative rating for WDC's 65C02. 20MHz would be very nice.

So my plan is, when I get the new 55MHz 640x480 display, to use it in my current wirewrap design with the latest schematic posted on this thread (I WILL be replacing the 'AC138 with an 'ABT20 dual 4 input NAND gate, 1 gate will address the EEPROM & SRAM and the other gate will address the display, I just need to find a PDIP version)... The old display I'll be using, since I know EXACTLY how it works, with a new wirewrap board using the XC9572 for memory decoding, since speed will not be the issue (successfully programming the CPLD will be the issue), I'll run it at 6MHz, and continue to update that project on the Fuel Injector Pulse Width Analyzer thread.

Any books you guys recommend for learning Verilog? I've got a few in mind already...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

This is the package I received today.... BS! 4 day delivery period. I paid for 2nd day air! UPS is garbage. The package was abused, then taped over. **** on those bastards.
Some may consider this off topic, but it is so VERY on topic IMO. Edit as you will.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

UPS is very expensive and not as fast as other services. When I had to ship a bike frame a couple of years ago, I found FedEx was half the price and twice as fast. Usually I use the post office which is also cheaper and faster than UPS. Many companies don't like to use it because it doesn't offer the tracking that UPS does, but in 17 years of our company shipping through the post office, they have never lost or damaged anything for us.

My experience with UPS has been nothing but stellar. Boxes shipped with clean, crisp corners with only the occasional crease in the cardboard. Always on time.

The package you received through UPS is exactly what I receive all the effin' time from USPS.

My experience with FedEx is similar to UPS.

Anyway, it sounds like UPS had accidentally dropped the box in the back of their truck or in the cargo hold of their aircraft. In any event, I would haul that box down to your local UPS depot and complain vociferously about it. If UPS doesn't know there's a problem, they can't fix it.

Was the package actually delivered by UPS, or are you in an area where they contract out the delivery to the USPS (for profitability reasons)?

Some time ago I read a write up of what happens inside a courier's automated hub facility - boxes are moving at outrageous speeds, and when they hit a support pillar or something, with more boxes piling up behind them, that's the kind of damage they get.

Can't find the write-up now.

No, I saw the poopie brown truck deliver the box. I intentionally did not open the door to greet the man, because I had nothing good to say. It was already 2 days late at that point and I knew he was just a cog in the machine. Then I saw the box after he left... I was livid. I was taking pictures, intending them as proof if I needed it. So I figured I would post one, sorry for all the expletives (which you don't currently see, heh). I had posted before I opened the box as I had expected damage, but there was none. I told my wife if she wants to pursue it, then she can get the refund. She had already called them and they agreed a refund was due because of the delay alone. As for me, that was the LAST time I use them, all I care about is my CPLD started board... I am at the bottom of that STEEP learning curve I have read about concerning CPLDs, but I have all the tools necessary to learn, so I'm divin' in.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Looks like Elmer the Elephant sat on it. Geesh!

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Way back when (40 years ago, to be exact), I was involved with the Postal Service's ZMT (ZIP Mail Translator) project. I was at the Oakland California sorting center cranking code into the ZMT when I heard something that sounded a bit like a train wreck. I got up, looked around and saw a massive pileup on one of the package sorting machines. It wasn't pretty. Some of the cartons were busted open and their contents were being mangled by more packages piling up. I'm certain to this day that some lady's underwear went flying past me.

By the time the postal drones got the machine stopped there had to be about 50 cartons in various states of disembowlment. I suppose UPS runs into that now and then.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

After a week of messing with the software, this morning I was finally able to implement the logic into the CPLD. No need to learn verilog, thank God. You can input schematics and the software does all the work to generate the files, including the all imprtant .JED file for programming. It is all extremely simple to learn. It took me so long because the first time I tried to compile the work, I thought it locked up, and I aborted the program, and unbeknownst to me it saved a schematic with bad instructions... I'll leave it at that, but I am extremely excited at all the prospects open now.

The glue logic is only using a small percentage the XC9572's pins and capabilities. Only 12% of the macrocells, 6% of the registers, and 45% of the pins... Now I can easily make the memory map more focused.

For sh*ts and giggles, the past (maybe) 15 minutes I designed a 16 bit preloadable binary counter with the 16 inputs latched, from 8 bits and a select, to save pins. I just picked 2 8 bit binary counters, 2 8 bit latches, and an inverter and wired it up. And BAM, it tells you all the pin assignments, top speeds, everything. For comparison, the counter used 48% of the macrocells, 46% of the registers, and 95% of the pins.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The ISE 9.2 software isn't perfect, but I've found as long as you have a schematic to work from, you can start a new project and enter the schematic fresh, and there won't be any problems. I've run into issues where I'll start modifying a schematic, and when I try to implement it, it gives netlist errors. Probably my fault but still, I have no complaints, I can get it to go through error checking and create the .jed file successfully...

Just to update, I'll post the final schematics with: discrete logic, the CPLD version that replaces the discrete logic, and the one with the SRAM window. None of it has been wired and tested, except for the discrete logic. I have some parts on order to implement the CPLD, so it'll be a couple weeks before I wire the last schematic up.

Discrete logic (old design):



Using XC9572 CPLD to replace the discrete logic (old design):


Inside the XC9572 CPLD utilizing all but 2 pins (new design,compare to original): This new one utilizes 21% of macrocells, 13% of registers, & 92% of pins... At this point, I would like to maximize pin usage.

EDIT: Added a divide by 2 and 4 from the FastClk input so user can hardwire a select from onboard divider to SlowClk. Fixed _DE00DEFF latch signal from address decoding to 5 bit flip flop from active low to active high (DE00DEFF). (Utilizing 23% of macrocells, 16% of registers, & 98% of pins)


Updated schematic to control a 16K memory window into 512K, using the CPLD logic from the last pic. Different Icons/Pictures, and Fonts will go into this space (right now my character fonts are occupying 4K out of the 8K EEPROM, and I am quickly running out of programming space)... It will be copied into faster RAM just like the OS, so the whole system can run @10MHz. I had to slow down the clock speed from 6MHz to 3MHz, to do the EEPROM to SRAM copy, due to the slow (150ns) 512Kx8 EEPROM. I'll be wiring it up in a week or two... (I ordered 2 oscillators 10MHz and 14.31818MHz, so the 10MHz and 3MHz speeds are not exact speeds on the schematic)

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Today I made a baby step and hooked up my XC9572 to the JTAG port. Not being very familiar with JTAG, I decided to wire up power to the CPLD and the TCK,TDO,TDI,TMS, and GND to the connector without hooking up VDD (I wasn't sure if it was VDDin or VDD out). After connecting the VDD, the software recognized the CPLD, erased it and programmed it, WOOO! Evidently the cable has an interface onboard...

Looking back, and for those interested, you just need the cheapie parallel JTAG3 cable ($12 from Digilent: http://www.digilentinc.com/Products/Cat ... ,395&Cat=5 ) and the Xylinx ISE 9.2i software (you have to register it, it's worth it), to get started with CPLD's. I am noticing now Digilent has their own software called Adept ( http://www.digilentinc.com/Products/Cat ... ,66&Cat=12 )which looks to be free as well. I'm gonna test it out and report back...

Working with Xylinx CPLD's has been VERY rewarding so far. I understand now why so many discrete logic IC's are disappearing. But now so are some of the faster older (32-84 pin ) CPLD's in PLCC form, the newer Coolrunner CPLD's (100+pins) seem to be available only in VQF type packages. Good luck soldering those...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The software only recognizes their newer, more expensive USB cable, so I couldn't test it.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502