This is what I did in my ARM2 project - on reset, the CPU is held in reset state while a counter ticks up driving the address bus, and ROM is copied to RAM. Then after that the CPU is let out of reset and runs from RAM only.

It's essentially a DMA operation, and it's very fast (one copy per clock cycle). The overall complexity on a 6502 would be something like a pair of flipflops, an 8-bit counter or two, and maybe a tiny bit of glue logic - I showed a possible circuit diagram for that cut-down version here: https://youtu.be/gA_D3plgqgI

Edit: adding a black and white copy here, sorry for the quality as I only have a low resolution snapshot now.

Instead of 65C51 as ZG6502 I/O device, a 65C22 may be a better choice. This way it can be configured to interface to compact flash or SD disk and load & run more sophisticated software. 65C22 is also a more versatile I/O that can even do serial I/O in bit-banging fashion. I believe zero-glue logic approach is still possible with 65C22.
Bill

Sorry, but I'm not sure I got how the Zero-Glue 6502 works....

On Reset I understand that the ROM is always active, in all the 64k, while RAM is active in the low 32k.
So, I can read without bus contention in the ROM area, but when I write to the RAM area, the CPU will have bus contention with the ROM output, doesn't it?

So, my guess is - and I've probably missed it in the discussion above - that the ROM in its lower 32k already contains a copy of the data that is copied to from the upper ROM area? Then CPU and ROM would output the same value, and not generate contention (depending on output voltages etc), right?

That also means that during this coexistence phase the lower 32k must not be read before it is written or otherwise the RAM and ROM outputs have bus contention, right?
After copying to the RAM, both RAM and ROM have the same value, and no contention occurs, right?

Very cool design!

_________________
Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Yes you are exactly correct. So let me explain in my own words which should match what you've said.

The EPROM data is duplicated in upper 16K as well as 16K from $4000-$7FFF. RAM's active-high chip select is tied to 6502's clock so when EPROM is copying data from its upper 16K to RAM from $4000-$7FFF, the same data already existed in EPROM. So it is true that EPROM is always enabled and driving the data bus while reading and writing, the data it wrote to RAM in the range of $4000-$7FFF is exactly the same data as already existed in EPROM. Another word, for the write operation both 6502 and EPROM are driving the same data out to the bus so there are no contention. The RAM is disabled until high phase of the clock where 6502's RWB force RAM's output buffer in tri-state mode, so again there is no contention caused by RAM.

One the 16K copying operation is done, program jumps to RAM area where both RAM and EPROM are driving the bus but with the same data. The program spin for enough time for reset supervisor to timeout and disable EPROM at that point RAM is solely in charge of the bus.

Bill