Here is the first iteration. It uses 3 dual pot rams now - one for the character value, one for foreground and one for background. So in the end you should be able to define foreground and background color of each character. It also sprouts basic ROM and 512 MB character RAM (simply because I have those chips lying around)

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No simulation survives contact with reality!

Again - it was a very long time since the last post - but the project is still alive. Actually it's better than alive, it's working. This is a test image of pure TEXT output.

Here's how it looks like on a breadboard:

I attached the schematics as well.

Now why did it take so long?

it was complicated - far more complex than I imagined

if you have only 30-60min each day at night when you are tired progress is slow

you don't have any time to yourself during Christmas vacation

you are bound to make many mistakes, and motivation to debug sometimes is low

especially when something works, than does not work next day

only after I discovered load from a logic analyzer might positively impact your design things became more stable

pull-up resistors are better stabilizers than load from a measurement device

happy hacking
Michael

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No simulation survives contact with reality!

Ha ha. Nice work. Regarding lack of time, I know the feeling, we often have other things to prioritise over our hobbies. But the hobbies are still there for us when we get back to them. Sometimes they even still work!

Mighty fine work!

Thanks Brad, actually I copied the Graphic part from your design

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No simulation survives contact with reality!

The PCB I created (and ordered from China) worked mostly. Here are both cards combined showing text output

and here doing graphics

There are 2 problems still. Column 0 of the text output is not 100% correct, some timings seem to be off. Far worse is an issue caused by the 4 Y address lines connecting the 2 boards. If they are directly connected via short pin headers the output goes black. If I connect them via 40cm wires as shown in the pictures it's working. Either reflections, or timings, or cross-talk is causing an issue here.
Still as "proof of concept" this worked out. But I probably would not repeat this exercise and instead use one or more CPLDs or even a FPGA for my next iteration. There are simply too many chips in this "bug cemetery"

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No simulation survives contact with reality!