Almost complete schematic for bits 0..7 of the address bus and everything driving it. Only thing missing are the LEDs and the OE/CLK control signals.

On the left is the AB bus (external address bus). The AB signals feed into the incrementer, and the output goes both to PCL register, as well as through buffer onto the the internal address bus AD. Also driving the AD bus can be: ALU, DB, or FA/FC/FE.

The data from the AD bus is stored in the ABL register, which goes out to external memory, and loops back to the left into the incrementer. All the blocks with a name in the middle are 8-bit registers, and the triangles are all tri-state buffers.

Output of the PCL register can also be driven onto the AI bus (Edit: just added it to schematic). The AI bus goes into the ALU.

The upper part of the address bus will be the same, except for different set of constant values.

And here's the updated board. I've added some labels to show what is what. The ABL/ALU circuit should be duplicated underneath for the upper half, plus a couple more buffers for the PCL -> AI and PCH -> AI paths.

Still need to add: P and IR register, DB drivers, the BCD muxes, and the blinkenlights. I have a strip of 0603 LEDs at the top to give an impression of the size. I may pull them apart a little bit more.

I've resized the board to half eurocard format (160 x 50 mm) so that I can see better what area I have to work with.

Schematic of the flag registers and selectors.

Because flags can be updated individually, I'm using dual D-flipflops (74AUP2G79) with individual clock inputs in VSSOP-8 package.

Input selection can be done with 2 ICs: a dual 4:1 mux (for C and V), and a quad 2:1 mux (for Z, I, D, and N). Note the grouping is organized differently in the schematic symbols.

There are 2 select lines, of which SEL_P0 is shared by both muxes. SEL_P1 is a don't-care for the Z, I, D, N flags

• SEL = 00, selects ALU output for Z/N/V/C flags, IR[5] for CLD/SED and IR5_BRK for the I flag (=IR[5] OR BRK)
• SEL = 01, selects DB output for all flags, used for PLP/RTI
• SEL = 10, selects BCD Carry = C OR ALU_C
• SEL = 11, selects IR[5]/0 for CLC/SEC/CLV

The outputs of the 6 flipflops go to a buffer which allows putting the P register on the databus for PHP/BRK. The "B" pseudo-flag comes straight out of the instruction decoding logic.

And here's the complete data bus with drivers and IR. I need to replace the IR with a different kind of register with reset input so I can use that for injecting a BRK instruction during interrupt/reset handling, but I don't have that symbol in my library yet.

Still need to do BCD adjustment mux into M register, and top half of ALU/AB (mostly copies of bottom half)

And here is schematic of the BCD adjustment. If the SEL_BCD signal is '0' then DB is loaded into the M register. If SEL_BCD = 1, then the BCD adjustment values are loaded, which can be selected to be 0 or 6 for each digit.

The M register feeds the second input of the ALU (as its only source). It is used for memory operands, for instructions like ADC and ORA. It can be optionally forced to 00 in the ALU, and this result can be optionally inverted to create a choice of: M, ~M, 00 or FF. The 00 option is used in combination with Carry input to implement an increment.

The first input of the ALU is either: A, X, Y, S, M, PCL, or PCH.

For BCD add/subtract, the M register is used for the memory operand in the normal cycle, and then loaded with BCD adjustment values in additional BCD cycle.

And here the updated sheet with all the registers.

Added buses to ALU sheet. I also copied that sheet for higher nibble, and copied ADL to ADH.

Board also updated, including some mounting holes.

This should be the complete datapath, minus the blinkenlights. I will put those on a different sheet by themselves.

As I said in first post, I will first make a prototype board with all the control logic in an FPGA. For convenience, the same FPGA will also serve as memory, clock generator, and UART peripheral. Most likely, I'll also add a couple of 7-segment displays for debugging, showing current address/databus values. All of that stuff will be placed below the datapath.

How many control lines will you need? And will they have LEDs too?

Looking at the board, I changed my mind on this. I am now planning to place a LED near each of the buffers and register showing the enable/clock signals, so it's clearer what each particular LED is showing.

I also think that I'm going to remove the IR register from the data path. It's not really doing anything there. I think it's better to put it in the control unit. For now, I'm just going to incorporate it in the FPGA.

I've made some more progress with the placement.

I have also modified the verilog code to reflect the implementation of the flag registers from the schematic so I could run Klaus' test suite again.

Sounds great!

Not easy finding a good place for the LEDs and hooking them up, but I think this would work.

Since the LEDs are wider than the chip, but I have some vertical space, I can do them in two rows above each other. The pads have vias in them, and the resistors (0402) are at the bottom layer.

Because the wiring is all criss-crossed, I need to use the VCC and GND planes to attach them. Fortunately, the top and bottom layers can take over the role of ground plane, so I think it'll be okay.

This is just a test, by the way. I'll rip this up, space them a little closer, and keep them centered with respect to the registers/buffers.

So you are doing 0402. Good luck!
It is possible with liquid solder, in order to make them stick, and low fan speed and high heat as I'm sure you know.

A few actually blew away in my last project. I was thinking of using a dab of super glue on the board b4 placing each 0402 in my latest project in order to get the process to 100%.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

No worries, I've done many hours of 0402 assembly. I use a reflow oven, and solderpaste stencil, so it's just a matter of setting the components in the paste.

While doing the LEDs, I realized that my flipflops and buffers are organized in such a way that LSB is on the left, and MSB is on the right. I simply followed the standard layout of the ICs.

For the LEDs, I want the LSB on the right. But I also want to line up the ICs with pin 1 on bottom left.

Since I have no interest in complicating routing any more than necessary, nor do I want to redraw all the schematics, and attach DB7 to Q0, I am simply going to redefine the pin connection in the IC. It's all arbitrary anyway.

Here's the cleaned up version. I first went back to library, and defined a special package for 8 LEDs in a strip with a white half-open box around them, spaced in 2 groups of 4. This makes it much easier to line up, because I don't have to worry about spacing the individual LEDs.

I've moved the LEDs a little closer together, just enough to snake 2 traces inbetween, but then pulled the two nibbles apart a little bit for visual clarity, but also for allowing the ground plane to fill between the two groups.