The drill diameter is listed as 0.02362205 (the outer layer diameter is 0.03962205 and the inner is 0.02362205). I assume that these are in inches, so we have 1mm outer, 0.6mm inner.
What values are recommended? I assume that I don't go as small as the minimum that PCBtrain will do, so would 0.9mm outer and 0.5mm inner do the job or should I go smaller? Those are the smallest settings listed by Eagle, although I can enter them manually and go smaller if I need to.

Thanks for pointing that out. I'd neglected to put in the 33pF capacitor between the crystal and ground .

I always use .015" holes with .035" pads for vias on .062"-thick board, and .008" holes with .028" pads for vias on .031"-thick boards, although as technology has improved, I could probably reduce that now. These are finished hole sizes. They start out by drilling them about .003" bigger, and the diameter decreases as the inside gets plated. Part of the reason for the size of the pad is just to prevent breakouts if the drill indexing is not perfect. Again though, they're getting better and better at it. If there is a breakout, you definitely don't want it on a side that a trace comes into the pad. Teardropping will help prevent that. I only use the .031" thickness for really small boards (like not much over postage-stamp size).

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I made liberal use of 0.026" diameter via with 0.008" holes in my POC board (0.062" thick), as well as on the host adapter board. I have not seen anything that would make me reconsider that decision.

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It depends on what you need. Going all the way to the limit may be a bit risky if PCBtrain doesn't verify your data. For instance, in Eagle, the DRC is based on finished hole size, but if PCBtrain specifies the annular ring based on drill size (which is slightly bigger), and don't check your data, then you may get bad results.

So, to stay on the safe side, you could add 0.1 mm to PCBtrain numbers (or more, if you don't actually need vias that small)

If you change Eagle to a metric grid, it will report all measurements in mm.

Here's my latest attempt at routing my board. There have been a few changes to the circuit itself: Instead of using a triple AND gate to deal with the IRQs and a series of NAND gates for the memory address decoding, I've incorporated all of these into a single GAL (the cost is in power as GALs can chew up 30-50mA at a time).
I've also gotten rid of the address bus, data bus and signals pin headers as routing to them was making my traces a little too long for my tastes.
The VIA now has 2 sets of pin header holes for port A and port B. This gives me the ability to put pin headers on one set and pin header sockets on the other. I was wondering it it's worth putting buffers in as well (between the VIA and the pin headers) ... or series resistors. Yes? No? Advice welcome .

With regard to the routing design: I hope this looks ok. To my own eye it certainly looks better than the version that the auto-router spat out!

No. For some things, resistors would cause problems. (Been there, done that.) As for buffers, they won't allow individual bits' data direction control like the VIAs' DDRA and DDRB do. You'll definitely need that for many things, in my experience. According to my tests, the 65c22 has very strong outputs anyway, many times as strong as the data sheet lets on. Additionally, WDC's '22 has bus-holding devices for input pins, so if they're not connected to anything, they will hold themselves at the last valid logic state detected, or if never connected, they'll pick one. A buffer you might add won't have that luxury.


Note that the row spacing of dual-row pin headers is .100", not .200". (That will save you some board space too.)
Power and ground still need to be connected to the ICs, unless they're connected in layers the picture doesn't show.
Since the ACIA's I/O is already going through the line drivers and receivers, you might want to just put a DB-9 right on the board, instead of the pin header.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I agree wholeheartedly!

Mike B.

I second Garth's opinion. The VIA's outputs are pretty robust and while they might not be able to drive a large relay coil, they can certainly deliver enough current to handle a lot of other loads. Adding resistors will merely get in the way, in my opinion.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Ok cheers; I'll leave VIA outputs as-is.

I've now managed to wedge the address and data bus pin headers in by moving them and I've added more pin outs to the VIA outputs (in case they are needed and because I've got the space there ). I've also moved the oscillator closer to the clock driver (IC3, D type flipflop).
With regard to power: The 2nd layer is GND and the 3rd is +5V so that's taken care of.



I think I'm almost ready to have the board made.

One thing which puzzles me is this:



This obviously shows the layers and their thicknesses. Should these be equidistant from each other? I.e. As the PCB that I'm going to be ordering is 1.6mm FR4, should it be 1.6 divided by 3 = 0.53mm isolation? And the copper thickness left at 0.35mm?

Also, I've put 1*2*15*16 for the layers. (layers 1,2,15,16). Is this correct? I think it is, but am not sure (I don't have any buried VIAs by the way).

Sorry to keep asking what might be somewhat basic questions: It's quite a chunk of money for me to have this made so I'm being super-cautious .

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I don't think the settings in Eagle are actually exported. You need to specify those separately. I wouldn't worry about that, though. If you don't say anything, the board house will use their default settings, which is good enough. Having custom settings can dramatically increase the price.

The layers don't have to be equidistant, but they do have to be symmetrical to avoid warping. Again, the board house should do that by default.

Your R8/C20 are a bit far away from the crystal pin. I would try to get them closer.

Thanks - I wasn't sure if the gerber files had this info or not. Good to know they don't.

As recommended, I've moved R8 & C20 much closer (see below) to the crystal.


Also, would it be best then to move the power to the south-central part of the PCB? I.e. :


Garth; you mentioned that I needed grounding pins for the bus headers for the ground return paths? I'm a bit confused. All the header pins do is allow my bus monitor to connect to the buses. The monitor will draw power from one of the sets of Aux Power Out pins on the board (currently in the south central area).