Garth, it sounds as if you're contemplating a new design... generation two of the Workbench Computer, perhaps? Early in this thread you mentioned the products from Data Delay Devices, and those seem intriguing indeed! Their variable delay lines are listed here: http://www.datadelay.com/asp/variable.asp

As these seem small and easy to work with, would you contemplate including a couple of these in your new machine? It seems a small price to pay for both researching the '816 timing envelope and achieving maximal timing for the new computer itself.

( For those new to this thread, maximal '816 timing is non-trivial, with interdependent issues of timing, bus contention, signal quality and power consumption. Also, the '816 datasheet lacks many of the pertinent bus timing specs, as noted in the lead post. )

cheers
Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Funny you should ask, Garth. BCS Technology recently acquired a new higher-end digital camera that takes exceptionally good photos, and has a wide focal range, from less than six inches to upwards of a mile (see attachment for just how close a closeup it can take). It should be able to take sharp pictures of 'scope traces, something that I had considerable trouble doing with my previous camera.

What I'd like to be able to do is figure out how to secure the camera to the bezel of the HP 1725 'scope we have on the electronics bench so photos are taken at close range without surrounding light interference. At one time, camera adapters for that purpose used to be readily available, but I haven't seen anything of the sort in recent years. These adapters held the camera at a precise position, minimizing image distortion caused by the lens not being dead square to the CRT face and eliminating blurriness caused by having shaky hands (that describes me these days ). They also included a hood that completely excluded surrounding light. Way back when in my bench technician days, I used such an arrangement to take Polaroids of 'scope traces for use in technical manuals.

Anyhow, I have been wanting to get a collection of 'scope images of the various signals on POC V1.1 for comparison to POC V2 when it gets built. So I will make the effort to get something as soon as I work out how to set up the camera for the purpose.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Nice, Garth -- I like how the duration of the 245's enable time is curtailed by the NAND pulse-shrinking circuit. That gives a bit of dead time to serve as a timing cushion and prevent bus contention between the 816 and the '245. But, as you know, a too-generous cushion will cause you to fall short of the 816's true performance potential, and that's where the variable delays come in. (I realize your diagram omits the variable delays units.)

If it's to be a quest for absolute max performance, I assume you'll also provide a means to experiment with clock duty cycles other than 50%. It'd be no surprise if actual (rather than documented) minimum pulse-width for Phase2 low differs somewhat from the actual minimum pulse-width for Phase2 high. Only experimentation will reveal this. Perhaps your clock oscillator should be made of two variable-delay units connected nose-to-tail in a loop. One delay unit would determine the Phase2-high time and the other'd set the Phase2-low time. (You'd need an inverter in the loop, too, but I'm sure you get the idea.)

Also on the absolute max performance checklist, remember to consider a FET bus switch such as 74bct3245 as a drop-in replacement for the '245. That'd be a tradeoff. The device has near-zero prop delay, which gains you some speed, but the gain would be reduced (or in a large system even reversed) by capacitive loading, which a FET bus switch won't buffer.

A FET bus switch could also be considered as a faster replacement for the '573 bank-address latch. We discussed this privately -- allowing the RAM address inputs to dynamically hold their state via capacitance. Pinout-wise you'd have to finagle things slightly but the '573 and 'bct3245 are both arranged 8-bits broadside, so it'd be doable -- especially if you're using one of these adapters to place the SOIC bus switch IC on a .1" grid.

-- Jeff
ps to BDD - I think the main obstacles to photographing an oscilloscope screen can be overcome with just some patience, a tripod, and a means to avoid reflections. This means keeping the camera and any other reflected-view objects in the dark or obscured from sight. A hood would do the trick... or we could take a masterful tip from Ford Prefect and use a towel!

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I have a potentially very stupid question about the Bank Address Latching Circuit on the first page (the one from the 65816 data sheet): Why is there a diamond in the middle of the BA/D data bus (second line from the bottom)? I know that symbol as "Controlled Voltage Source" (see http://www.rapidtables.com/electric/ele ... ymbols.htm) which really doesn't make sense.

Best guess: it was an attempt to indicate that the bus is bidirectional at that point. I didn't really notice it, but I don't recognise it as a convention.

Someone on this forum who started another thread on the '816 considers this a hardware bug, though I'm not sure I agree. Arlet's point: Does the '816 predate the 'C02? Something I've noticed about the datasheet though. Page 52, Section 7.5 states that invalid addresses are only generated during a specific low-byte index-addressing internal addition that is propagated to the external buses. Based on the following snippet:

BA0-7 and A8-15 are invalid. According to footnote (4) of Table 5.7, invalid addresses are only generated in Emulation mode or when X=1 in Native mode (8-bit index), and ONLY during a write or page boundary crossing (presumably the extra cycle to fix the NMOS 6502 page boundary bug). I interpret this as: if X=0 and is left alone after native mode init, VDA/VPA need not qualify a memory access, resulting in less propogation delay for a discrete design.


I hope that's wrong, tbh. For a DMA controller, cycle-steal or transparent DMA honestly would be easy to implement (note to self- don't use Verilog) thanks to those control signals.

On an unrelated note: Footnote (1) of Table 7.5 says to add one cycle if EITHER M or X=0. Many of these instructions, however, show the extra cycle being added only due to 16-bit accumulator (M=0) and not due to 16-bit index. Has anyone tested whether the extra cycle for such instructions is added when M=1 and X=0? Indeed, there are instructions where having X=0 vs X=1 matters- Footnote (4). I guess the logic is the the '816 actually loads all 16-bits of the accumulator during reads, even when A is 8-bit. But this doesn't explain an extra cycle for writes when M=1 and X=0?

If the 816 reintroduces some inconveniences of the NMOS 6502 which the C02 fixed, might that be because Apple and Mensch were working together to make a highly compatible micro, for use in what became the IIgs? Mensch said: "In the case of an Apple computer, as an example, the way that [Apple co-founder Steve] Wozniak did his disk controller, we had to make modifications because of the way that the disk controller works."

Cheers
Ed

The data sheet's wording often seems to be contradictory in trying to explain when invalid addresses are generated. The best thing to do is consult the operations table starting on page 38 of the data sheet.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I am quite late to the party. But I have a question.

Yes, it is clear that even using a transceiver in the data bus there could be contention. But, we have some ways to inhibit 65816 driving the bus, right? Would it be possible to use the
BE (Bus Enable) signal to prevent it to drive the data bus with bank address once it has been successfully latched? Thanks to that, you have some grade of control to avoid contention between bank address and memory reads.

Is that wrong?

Edit: I initially said RDY signal, but I meant BE.

Just for reference, from 2015:


My feeling is that this is saying that RDY is a synchronous input sampled on the usual falling edge of the clock and affects the subsequent phase: it's not the Bus Enable input BE (which I'm guessing is async... but really ought to check!)

AFAIK, BE is asynchronous and simply tri-states the appropriate pins.

I think of RDY as simply controlling whether the next Phi2 falling edge is effective on the CPU. If RDY is low, then Phi2 is internally held high, and this is externally visible on the '816 due to the bank address multiplexing.

In order to halt the CPU for a DMA access, it's necessary to use both BE and RDY. RDY to halt the CPU (so it doesn't crash due to bogus data on the bus), and BE to allow the DMA master to drive the address lines.

Yep, my fault. I said RDY, but I meant BE (Bus Enable).

BE does not interrupt the CPU at all. It just makes the CPU to stop driving the address and data buffers. Once the memory controller latches the bank address after PHI2 rise, it could also deactivate BE. And hence ensure the data bus will be free for the memory to write the read result. It can activate BE back again a while before PHI2 fall edge. Which is the instant when the CPU will read the data bus.

Something like this might require 3 different clock signals at the same frecuency but shifted a little bit in time. Let's call them A, B and C. Using a shift of 10ns would be okay according to the timing diagrams. This is something that could be obtained with a 74HC04 part. B could be the clock input for the CPU. C is 10ns ahead in time, and A is 10ns delayed.

On the rise edge of B, the bank address is latched. On the rise edge of A, the BE signal is deactivated, the memory request signal (some sort of Memory Address Strobe) is also activated. This means the CPU stops driving the data bus 10ns after PHI2 rise. And memory chips are still not selected. Thus, there is no bus contention there. On the fall edge of C, BE is enabled again. This is 10ns before fall edge of PHI2. And the memory IC must have written the data at this point in time (memory access time must be below 15ns).

For the hold times, something similar can be done. On A fall edge, the memory OE signal is deactivated. This is 10ns after PHI2 fall edge. So the hold time of the read byte is ensured.

Does it make any sense?

I might be missing the point of what you're trying to achieve here. It sounds overly complicated compared to using an external tristate buffer and doing DMA during Phi1.