This post turned into a kind of stream of consciousness troubleshooting log. I started out intending it to be an update, but then I kept thinking of things I wanted to try, and writing down the results. I'm going to go ahead and post it as is, because I'm too tired to try and edit it into anything entertaining! The short version is, I made some progress. All this troubleshooting has uncovered a few mistakes that I've corrected, but the main problem is still there. That main problem seems to be that the board freaks out whenever there's a "LDA 0,x" instruction. It does not freak out when there's a "ROL 0,x" instruction. I don't know what this means. I guess tomorrow I'll have to put together a test to see what addressing modes make it freak out. If there's bus contention reading from RAM, I would have thought that read-modify-write instructions would also cause it to happen. Anyway, if anyone feels like slogging through all this, I'd be grateful for advice!
Well, I have definitely made some progress. I'm not sure what it all means. I redid the VCC/GND connections for the DS1813 and the 74HC163, and added another bypass cap. RESET\ still looks a little bumpy, but it's better, and I don't *think* I'm getting glitchy resets any more. I'm not sure what I'm getting. Like I mentioned earlier, I copied BDD's ZP RAM test from that other thread:
Attachment:
File comment: I didn't copy BDD's comments... if you want to know how it works, you should go read his code!
ramtest.s [1.22 KiB]
Downloaded 43 times
I'm still not able to get good results with the -ifclk mode of fx2pipe. However, the -a mode seems to work fine:
Code:
paganini@Ariel:~/6502$ fx2pipe -a -n=32k >capture1.bin
paganini@Ariel:~/6502$ decode6502 -ahisy --mem=00f --phi2= --rdy= --rst= --vecrst=8080 capture1.bin >capture1.txt
Attachment:
capture1.txt [310 KiB]
Downloaded 20 times
Code:
paganini@Ariel:~/6502$ head capture1.txt
???? : : RESET !! : 7 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=1 Z=? C=?
8080 : A2 00 : LDX #00 : 2 : A=?? X=00 Y=?? SP=?? N=0 V=? D=? I=1 Z=1 C=?
8082 : 8A : TXA : 2 : A=00 X=00 Y=?? SP=?? N=0 V=? D=? I=1 Z=1 C=?
8083 : 38 : SEC : 2 : A=00 X=00 Y=?? SP=?? N=0 V=? D=? I=1 Z=1 C=1
8084 : 95 00 : STA 00,X : 4 : A=00 X=00 Y=?? SP=?? N=0 V=? D=? I=1 Z=1 C=1
8086 : A0 09 : LDY #09 : 2 : A=00 X=00 Y=09 SP=?? N=0 V=? D=? I=1 Z=0 C=1
8088 : 36 00 : ROL 00,X : 6 : A=00 X=00 Y=09 SP=?? N=0 V=? D=? I=1 Z=0 C=0
808A : 88 : DEY : 2 : A=00 X=00 Y=08 SP=?? N=0 V=? D=? I=1 Z=0 C=0
808B : D0 FB : BNE 8088 : 3 : A=00 X=00 Y=08 SP=?? N=0 V=? D=? I=1 Z=0 C=0
8088 : 36 00 : ROL 00,X : 6 : A=00 X=00 Y=08 SP=?? N=0 V=? D=? I=1 Z=0 C=0
You can see it's executing the right code. It works fine for a while, and you can see .X counting up as it scans through RAM. But then it freaks out:
Code:
80A8 : D0 EC : BNE 8096 : 3 : A=FF X=3B Y=00 SP=?? N=0 V=? D=? I=1 Z=0 C=0
8096 : A9 FF : LDA #FF : 2 : A=FF X=3B Y=00 SP=?? N=1 V=? D=? I=1 Z=0 C=0
8098 : 95 00 : STA 00,X : 4 : A=FF X=3B Y=00 SP=?? N=1 V=? D=? I=1 Z=0 C=0
memory modelling failed at 809A: expected A0 actual 7D
memory modelling failed at 809B: expected 09 actual 7D
memory modelling failed at 809C: expected 36 actual 7D
809A : 7D 7D 7D : ADC 7D7D,X : 4 : A=7C X=3B Y=00 SP=?? N=0 V=0 D=? I=1 Z=0 C=1 prediction failed
memory modelling failed at 809D: expected 00 actual 7D
memory modelling failed at 809E: expected 88 actual 7D
memory modelling failed at 809F: expected D0 actual 7D
809D : 7D 7D 7D : ADC 7D7D,X : 4 : A=FA X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0 prediction failed
memory modelling failed at 80A0: expected FB actual 7D
memory modelling failed at 80A1: expected B0 actual 7D
memory modelling failed at 80A2: expected 10 actual 7D
80A0 : 7D 7D 7D : ADC 7D7D,X : 4 : A=77 X=3B Y=00 SP=?? N=0 V=0 D=? I=1 Z=0 C=1 prediction failed
memory modelling failed at 80A3: expected F6 actual 7D
memory modelling failed at 80A4: expected 00 actual 7D
memory modelling failed at 80A5: expected D0 actual 7D
80A3 : 7D 7D 7D : ADC 7D7D,X : 4 : A=F5 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0 prediction failed
memory modelling failed at 80A6: expected 0F actual 7D
memory modelling failed at 80A7: expected E8 actual 7D
memory modelling failed at 80A8: expected D0 actual 7D
80A6 : 7D 7D 7D : ADC 7D7D,X : 4 : A=72 X=3B Y=00 SP=?? N=0 V=0 D=? I=1 Z=0 C=1 prediction failed
memory modelling failed at 80A9: expected EC actual 7D
80A9 : 7D 7D 7D : ADC 7D7D,X : 4 : A=F0 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0 prediction failed
80AC : 7D 7D 7D : ADC 7D7D,X : 4 : A=6D X=3B Y=00 SP=?? N=0 V=0 D=? I=1 Z=0 C=1
80AF : 7D 7D 7D : ADC 7D7D,X : 4 : A=EB X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0
It's nothing but 7D for ages. Then, suddenly, it changes to a different kind of junk:
Code:
83FD : 7D 7D 7D : ADC 7D7D,X : 4 : A=DD X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0
8400 : 55 55 : EOR 55,X : 4 : A=88 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0
opcode 57: cycle prediction fail: expected 1 actual 5
8402 : 57 : ??? : 5 : A=88 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0
8403 : 55 15 : EOR 15,X : 4 : A=FF X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0
8405 : 55 55 : EOR 55,X : 4 : A=AA X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0
8407 : 55 77 : EOR 77,X : 4 : A=F4 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0
8409 : 55 5D : EOR 5D,X : 4 : A=81 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0
840B : 55 55 : EOR 55,X : 4 : A=D4 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0
840D : 55 45 : EOR 45,X : 4 : A=A5 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=0
840F : D5 55 : CMP 55,X : 4 : A=A5 X=3B Y=00 SP=?? N=0 V=1 D=? I=1 Z=0 C=1
8411 : 55 55 : EOR 55,X : 4 : A=F0 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=1
8413 : 55 55 : EOR 55,X : 4 : A=A5 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=1
8415 : 55 55 : EOR 55,X : 4 : A=F0 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=1
opcode 57: cycle prediction fail: expected 1 actual 5
8417 : 57 : ??? : 5 : A=F0 X=3B Y=00 SP=?? N=1 V=1 D=? I=1 Z=0 C=1
8418 : D5 5D : CMP 5D,X : 4 : A=F0 X=3B Y=00 SP=?? N=0 V=1 D=? I=1 Z=0 C=1
It does that for a while, the finally bombs out with:
Code:
8801 : 00 00 : BRK #00 : 7 : A=FB X=3B Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F004 : 40 : RTI : 6 : A=FB X=3B Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
8803 : 00 00 : BRK #00 : 7 : A=FB X=3B Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F004 : 40 : RTI : 6 : A=FB X=3B Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
8805 : 00 00 : BRK #00 : 7 : A=FB X=3B Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
F004 : 40 : RTI : 6 : A=FB X=3B Y=00 SP=?? N=1 V=0 D=0 I=1 Z=0 C=1
for the rest of the capture.
*HOWEVER*
If, without resetting the 6502, I immediately do a second capture, I get:
Code:
???? : 38 : SEC : 2 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
???? : 4C 00 A0 : JMP A000 : 3 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
A000 : 38 : SEC : 2 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
A001 : 4C 00 A0 : JMP A000 : 3 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
A000 : 38 : SEC : 2 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
A001 : 4C 00 A0 : JMP A000 : 3 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
A000 : 38 : SEC : 2 : A=?? X=?? Y=?? SP=?? N=? V=? D=? I=? Z=? C=1
which suggests to me that the garbage in capture1 represents the capture failing somehow. Clearly, the 6502 has completed the RAM test and is sitting in the result loop, as it's supposed to be. On the other hand, the result loop is one of the failure loops for bad RAM. Is it possible I actually have a bad RAM chip and that it is, somehow, freaking out the capture when I run into the bad spot? I don't know. I ran some more captures. They all fail at *about* the same place: .X = 37..3D. I also tried using a very slow clock (500Khz) and got the same results. At this point, I think I need to try a different RAM chip. I have a couple of spares, so... nope. Same thing, it bombs out at X=3C. This time, however, when I do my second capture, it's still spewing garbage! (55, 55, 55, 55, 55, with the occaisional 7D thrown in).
Well, is it something about that specific area of the address space, or is it something to do with how long we've been running? Let's tray starting .X at $35 and see how far we get. Aaand, it crashes immediately at LDA 0,X when .X is $35. That's something then. Wait a minute, I never tied off all those unused inputs on the `14, because I wasn't using it when I/O was in zero page. But then I moved IO into ROM so I could do the RAM test. (10 minutes later) OK, that's something. The decoder now has no "prediction fails." But this still happens:
Code:
808B : D0 FB : BNE 8088 : 2 : A=35 X=35 Y=00 SP=?? N=0 V=? D=? I=1 Z=1 C=1
808D : 90 1E : BCC 80AD : 2 : A=35 X=35 Y=00 SP=?? N=0 V=? D=? I=1 Z=1 C=1
808F : B5 00 : LDA 00,X : 4 : A=35 X=35 Y=00 SP=?? N=0 V=? D=? I=1 Z=0 C=1
8091 : 55 55 : EOR 55,X : 4 : A=60 X=35 Y=00 SP=?? N=0 V=? D=? I=1 Z=0 C=1
8093 : 55 55 : EOR 55,X : 4 : A=35 X=35 Y=00 SP=?? N=0 V=? D=? I=1 Z=0 C=1
8095 : 55 55 : EOR 55,X : 4 : A=60 X=35 Y=00 SP=?? N=0 V=? D=? I=1 Z=0 C=1
Could something be wrong with A4? When I beep it out it seems to go everywhere it's supposed to, and not other places. It seems like any read from $8090 - $80FF returns 55. That's about the same size as my I/O window. Once it gets out of the $8090-$80FF area it starts behaving properly... All those BRK / RTI is what it should really do when reading from that area of the ROM (it's full of zeros). And when it eventually works through all those it runs into the "RAM FAIL" loop at $A000.
I can test this really easily by having my reset vector start later in the ROM.
No that didn't fix it. There are still lots and lots of $55s, and this time when it read over $A000 and $B000 it didn't see what's in the ROM, just $55. It didn't start seeing what's in the ROM until $C000.
I went and checked all the wiring for yet another time. I would start to think maybe my ROM is bad, and just randomly freaks out and spews garbage, *except,* it always seems to happen after the instruction "LDA 0,x." That seems like bus contention. But why wouldn't it happen after ROL 0,x?