I'm terrible at estimating how much time it will take to do something. The tedious part is that I'm always trying to fit everything like a puzzle to make maximum use of board space. No bare-board space on the component side. Sometimes I find I have to move a component over by .002" to get a trace in, which requires moving the next component, and so on, rippling through, because I didn't foresee something.


You'll find lots of tips like this in the "Tip of the Day" column, at viewtopic.php?f=7&t=342 . Others are in the 6502 primer.


It's pretty easy. I'm always looking at the X/Y numbers at the bottom of the screen. Pressing "O" sets the origin for measurement wherever the cursor is, so moving to another point tells the X and Y distance to that point. Pressing the cursor keys goes .001" at a time if you don't hold one long enough for auto-repeat. The corner keys on the number keypad (which I never keep in number-lock) moves the cursor at 45° angles. An easy way to verify that a trace will fit through a tight space is to press two keys to increase its width by the amount you want the space to be, and and see if the trace overlaps anything. I use the keyboard constantly when laying out PCBs. It's not just a mouse activity.


Often it's nice to have the option to solve problems in ways the writers of the CAD software did not anticipate the user doing. One reason I like my old, cheap CAD is that it doesn't try to second-guess me and tell me, "You can't do that!" like OrCAD did at my last place of work, where I always wanted to tell it, "I know what I'm doing, and I have a plan. Just do what I tell you!" Part of it is this: I've mentioned several times that there are a lot of tricks you can pull if you know the gerber "language." Gerber files are plain text, and you can edit them with a text editor. Even with a cheap, simple CAD, you can for example use a layer which, instead of being copper, will be for "anti-copper," and copy and paste that file into a copper layer's file, putting it between %LPC*% (for "layer polarity clear") and %LPD*% (for "layer polarity dark") commands after laying down copper, possibly before laying down more copper. Now you can use this "anti-copper" layer to shave a little bit off a pad for example, to squeeze another trace past it. I add comment lines (which start with "G04") in the gerber file to tell what I did.

If there's an NC pin (or a pin you won't use) on an IC and you need its space to get another trace through, you can go ahead and route the trace where you want it, and then remove the line in the gerber file that put the pad in the way, and you won't have to make another version of the PCB component that lacks that pad. (If it's a thru-hole component and you eliminate the hole too, you'll have to cut that lead off when you assemble the board, which may not be cost-effective for production, but it's no big deal if you're building only a few boards. If it's SMT, don't forget to remove the pad from the soldermask and solderpaste files.) There are all kinds of tricks like this that you can do. I always re-check everything with the gerbv free gerber viewer software anyway before sending files to the board house. Edit, 12/1/16: I see there's a free 3D online gerber viewer at http://mayhewlabs.com/3dpcb .

The RS-274X standard that I printed out for myself is no longer at the URL I got it from, but http://www.artwork.com/index.htm has lots of gerber resources. Maybe it's hiding there. http://www.artwork.com/gerber/appl2.htm has the basic D codes. http://www.artwork.com/gerber/274x/rs274x.htm tells about converting the old 274D standard to the newer, more capable and more foolproof 274X standard.


The ones I've seen are pretty lame. Just practice and practice.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

When I need to make a compact board, I use QFN, TQFP and 0402 parts. That's always been good enough. In rare circumstances I may consider drawing a new shape to remove unconnected pins, but I'm not going to mess with the gerber output. Too much chance something goes wrong when I need to make a revision to the board a year later.

So far the boss has not allowed me to go below 0402 parts. 0402 does save a lot of space compared to 0603, but you can't run a trace between pads of the 0402 like you can the 0603, and vias take space too, unless you can put them under the SOT-23's, ICs, etc.. You could put a trace between pads of an 0402 if you are allowed to go down to .003"/.003" trace/space, but I'm not. The tiniest ICs don't let you run traces between pads either.

I had a situation a few years ago where I had to use an 8-pin DIP to get all the parts on the board, because the SO-8 actually took more room. How? Because I could put chip resistors and capacitors under the 8-pin DIP, but not under the SO-8.

I put notes on the board layout, outside the perimeter of the board so it's only visible in the CAD. I also put comments in the gerber files if I edit them. This keeps things clear if I have to come back to it later to make a modification. That need is rare though.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

For which there is no need.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Removing the phi2 qualification from RAM CS and adding it to the WE signal requires additional logic, for no practical benefits in this design.

Okey dokey. I've created a copy of my eagle copy and have restarted the routing on that. I've set the grind to 0.05 inch standard and 0.0.125 inch when using the ALT key. The track width has been reduced to 0.01 inch and I can now fit two traces between pads.


I'd attach a screen shot, but have received this message when trying to: "Sorry, the board attachment quota has been reached."
I wonder if I need to go back and start deleting stuff? I'd rather not as it'll make things look odd.

The forum software reached its default global size limit for all attachments. I increased the limit significantly so it should accept attachments again.

_________________
- Mike Naberezny (mike@naberezny.com) http://6502.org

Thanks Mike - much appreciated. I'll try and keep the attachment sizes down in the future.

... and speaking of, here's my almost fully routed board. In GIF format this time . I need to sort out some of the angles that the traces are running at just so that it looks a bit better and then do a review to see if there are any better paths for the longer traces. As ever, the thin yellow lines are the yet-to-be-routed traces, the red lines are on the top layer, the blue are on the bottom layer and 2nd layer down is the GND plane and the 3rd is the power plane.

One thing to be said on the subject of layers and power/GND planes: I was listening an episode of the Amp Hour who were interviewing a guest (forgotten his name-will track that down and post it) who said that having them in the middle wasn't the best as fabs are known to insert extra layers between them which can muck things up and also the VDD/BND pins of the ICs have to penetrate and route power through all of the layers of the board. This also includes the bypass caps.



Found it: Eric Bogatin. The entire interview can be found here: http://www.theamphour.com/252-an-interv ... mb-tenets/
The part where he mentions the power/GND planes is at 47 minutes in.

Keep in mind that these guys are talking about boards that run in the hundreds of MHz at the lower end. The effects that are related to the depth of the power/ground planes are an order of magnitude less than the effects of using DIP packages (or even PLCC/TQFP packages). Here is what a DIP package looks like on the inside:

All power and signals need to traverse those big lengths of wire inside the package to get out. Once they are out, it doesn't matter much if they have to travel another half millimeter to reach the right plane.

Also, looking at the picture of the lead frame, it is clear why IC manufacturers started to move the power/ground pins to the center of the package, rather than the corners. The distance to the center pins is much shorter.

You make a very sensible case, Arlet. Thank you for explaining in a way that even I can understand.

Mike B.

Thanks for clearing that up. I got a little concerned, although the majority of what I've been finding says that the power/GND planes should be in the middle.

On a slightly different note; the DRC check in Eagle is complaining that my traces are too close to the pads when I put two traces between pads at a time. From what I can figure out, the distance between the tracks the pads is about 0.2mm. This seems awfully close to me. What do you guys think?
Here's a picy. The traces are 0.01 inch (0.254mm) and the pads are for a standard DIP package spacing.

On a 4 layer board, they should always be the two inner layers, so that is not the issue here. What they were talking about was the thickness of the layers, the so called "layer stackup". See for instance my regular board house: http://eurocircuits.com/images/stories/ ... 010-v2.pdf

In the 4 layer board, there's a 14 mil (0.36mm) separation between copper 1 (top) and copper 2 (ground). Ideally, you'd want this layer to be thin so that the ground plane is close to the signals. But some board houses make this layer thicker, so that the ground plane ends up closer to the middle of the board, which is less ideal.


When you click on the DRC icon, it pops up a dialog with several tabs. You need to go to the "clearance" tab, and fill in the minimum distance. There are also other tabs with other measurements that you can fill in. Ideally before you start routing, you need to pick the company that's going to make the boards, and check their web page for information about their minimum trace/space/hole size/pad rings, and other parameters, and copy those to the Eagle DRC.

For instance, here's the table for Eurocircuits: http://www.eurocircuits.com/clientmedia ... -final.pdf

As you can see, 0.2mm would be what they call "pattern class 4", and is still fairly big. I usually go for pattern class 6, which they offer for the same price. For pattern class 7 and higher, they charge more.

Thanks, Arlet. I had already made some changes to Eagle's design rules, but given the starting values (8mm) and what I'd gotten down to (0.2mm) I thought it best to check.
I'm looking at getting my board manufactured by PCtrain and it seems their minimum is 0.125mm (http://www.pcbtrain.co.uk/resources/pcb ... apability/) which seems ok.

I see PCtrain also has minimum drill of 0.2 mm. Your vias seem quite big, so you may want to consider making them a bit smaller if you need some more room.

By the way, in your image showing the clearances, I noticed that the crystal is grounded on one side. I don't think it's supposed to do that.