The ones in the jar would have been dated 1975.

And, as I recall, they didn't actually sell any of the bad parts.

They were at the bottom of the jar to make it look like they had a large inventory of parts when in reality they only had a few.

I bet that jar of duds would be worth more now than they could have ever imagined!

Vulcan-74 Status...

I have been traveling a lot lately, but should get back to working on Vulcan-74 next month.
Having a lot of time to think about this project, I have made some decisions on where it will go next.
The overall design of the Audio and Video systems remains unchanged, and they are very close to completion.

Initially, it was to be a 6502 only project, but after learning about WDC's "catch and release" attitude towards hobbyists, I decided to make it a "universally compatible" platform that would allow any host processor, micro-controller, or FPGA to talk to it.

Recently, Atmel was gobbled up by Microchip, and since I have for the most part been a loyal AVR Fanboy, even the future of what I consider the best 8 bit platform is now in question. This got my wheels turning again... why have any CPU at all??!

After all, one of the main goals of this project was to carve something amazing our of the most commonly available and dated bits available, and so far that goal has been met and exceeded by a wide margin. The entire system is made of only the most common 7400 logic, and these parts will probably be available from multiple sources long after my shelf life expires.

So my new goal is to design a custom CPU for Vulcan-74, but to do so using ONLY the 7400 logic I have already used!
Like before, there will be no oddball parts or parts that ain't available at Digikey and the other big box suppliers.
The CPU will be tailored to the Audio and Video system, and have enough power to do some serious work.
For processing power, the Vulcan-74 CPU I am working on will be able to seriously outperform a 65C816 in this application.
I have never tried a homebrew CPU, and do NOT intend to look at what others have done to make my learning curve easier.
Knowing zippolla about this venture will mean that I will have to really push my ability and might even come up with something new!

I will detail my design goals for this next phase very soon, and have started an emulator / assembler to test my theory of operation.

This project will most likely continue on a dedicated Website as well, as I really want to put some detail into the posts, including the previous posts.
Since the "rewrite" will probably have 200+ photos up to this point, it only makes sense to move it to a proper home.

So once I have my CPU design goals carved in stone, I will launch Vulcan74.com and report back here to launch it.
No doubt, the complexity and chip count of this project will skyrocket, but it's going to be fun!

Cheers and thanks for this great community!
Radical Brad

Did you decide if it would be RISC or CISC?
Harvard or VNA?

And if CISC, won’t you be using modern ICs for storing microcode like NVRAM for example?

or ARA (addressable-register architecture), as Bill Mensch calls the '02/'816, neither RISC nor CISC?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Since I have only glazed over what others have done, and have never tried creating a CPU before, I would imagine mine would be...

"CRISC Von-Harvard" architecture!

I actually do have a plan, and am just working it out on paper now. It has changed many times over the last few days.

I will be using a 64K "Instruction Memory", made of triple high speed SRAMs set up like a 24 bit SRAM.
Program data will come in parallel as... Instruction, Operand1, Operand2.
I originally had more code space, but since it will be PURE code, 64K will keep it more retro.

There will be a 64K "Register Memory", that will function much like the memory of the 6502.
RegMem will be used via working register with INC, DEC, CLR, and compares.

There will be a 256 Byte IO Space that directly relates to the current Vulcan-74 Hardware.

There will be high speed math lookup SRAMs for Add, Subtract, Multiply, Divide, and Sine.

On bootup, all of SRAMs will be stuffed from a serial eeprom of flash memory (Cartridge)...
the Sprite, Playfield, Sound, Math, and the 64K Program memory.

Using no ROMs or ancient 74LS ALU chips along with the parallel operation will mean speed speed speed!
Having all 10ns SRAMs and 74HC logic "should" allow the Vulcan-74 CPU to outperform the 6502 or 65816 in this application.

The Instruction Set is a work in progress, and will probably be a mixed style of of AVR and 6502.
There will also be Dedicated Registers to address the Graphics and Sound Memory.

Most likely, I will rip up the small bit of circuitry I had put down on the Sound Generator and start the CPU.
To be honest, the Sound Generator was not challenging enough, and I was getting a bit bored!
Once I have a custom CPU, the desire to finish it all will be stronger.

Will post some sketches when I have time.

Cheers,
Radical Brad

I have those and more, pre-calculated at http://wilsonminesco.com/16bitMathTables/ , in the form of Intel Hex files. The info for using them and how they were calculated is all there too. And yes, that's the way to get a speedup of hundreds of times. There's no interpolation involved in using them, because the answer to every possible 16-bit input is already there, pre-calculated, accurate to the last bit. In the case of inversion, the answers are 32-bit in order to get the same precision throughout the whole range, although you don't always have to use all four bytes.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Nice writeup you have there!
I already have my tables and a loader done from a past project, so I am good there.
Used an AVR to load data into 512K SRAMs for my tables, but for this project, they will end up in the external Cartridge Memory.
Last time, I segmented the 20 bits of addressing as two 8 bit inputs, and 4 bits to select page (function).
This is one of the reasons why my HomeBrew CPU will hopefully womp a 6502... 16 bit math results in 10 nanoseconds!
Getting 3 bytes from the program memory each cycle will help as well. Kind of like comparing AVR to PIC.

Now on to the most difficult part... figuring out what I actually want for a hardware design.

Thanks,
Brad

After more notepad scratching last night, I decided to make the Vulcan-74 CPU with a 32 Bit wide Program Counter instead of 24 Bits.
My goal has always been performance over chip count or cost, and this seems to offer a good advantage.
Although the propagation through 5 74HC163 counters will be longer than 4, the parallel advantage is higher.
Avoiding a PIC style WREG or 6502 style Accumulator will greatly increase speed and code density.

As I laid out pathways between the 64K Register Memory and Math Memory, this became evident.
For instance, with a 24 Bit Wide Program Memory, this is the sequence to add 13 to a Register...



With a 32 Bit Program memory fetching 4 bytes at a time, the hardware becomes simpler and faster...



Doing a compare is also faster, and not dependent on a PIC style Working Register or 6502 style Accumulator...



So besides the extra propagation of one more 163 counter, the advantage of 32 Bit wide Program Memory over 24 Bit is clear.
This also puts my Program memory back up to either 512K or 1024K rather than only 64K.
It did seem a bit lacking to have 65536 General Working Registers (RegMem), and only 64K of Code Space!
Jumps can access up to 16MB of code space, so any jump is also a single cycle...



So here are the proposed specifications that I intend to turn into hardware next month...

[Vulcan-74 Pule Logic CPU]
Program Memory : 1024K with 32 Bit Output (INS,OP1,OP2,OP3)
Register Memory : 64K with 8 Bit Output (65536 General Working Registers)
Math Memory : 1024K with 16 Bit Output (Add, Sub, Mul, Div, Sin, Rnd, etc)
Cartridge Memory : External 8-64MB Serial Flash with "KickStart" Boot Code.

The "KickStart" code will fill the Program and Math Memories on Bootup and then give the CPU control.
From there, the CPU can access the Flash to fill Graphics and Sound Memories as required.

For development purposes, I am going to use only 15ns 32K SRAMs until I have the timing working perfectly.
At that point, I will rewire the entire CPU board using the 10ns 512K SRAMs and crank up the clock until failure.
If the CPU starts to self implode at say 13Mhz, then I will drop it back down to 8Mhz to be safe.
I did this with the 32MHz Playfeild Generator, which ran up to 40MHz, glitching at 42MHz.

It will be difficult to compare this CPU with a 6502 as it is completely dedicated and designed for the Vulcan Hardware.
Whereas the 6502 might run at 16Mhz, it would need say 20 cycles to tell the Sprite Generator to move Mario 2 pixels.
The Vulcan CPU on the other hand will do the same thing in 1 cycle, and run an auto compare on the last XY position.

To test performance, I actually have my own test that I use on every Video System I make called the "Got Balls Test".
How many 16x16 Sprites (with Alpha Pixels) can a system move at 60 frames per second? That is the magic number.
When I had the AVR talking to V74, I was getting 160. With the 6502 running the same test, it managed to pull 80+ Balls.
I fully expect the Vulcan-74 CPU to push 256 Sprites with no issues since it's brain will be hardwired to the main board.

Ok, let the Journey begin!
No doubt, there will be moments of frustration, confusion, and then jubilation.
Hope I don't need a bigger board!

Later!
Radical Brad

Woow...

Really interesting project.
Maybe one day I'll get smart enough to design my own CPU, until then I'll stick with the development boards...

Keep us updated...

Thanks, hopefully after this endeavor I too will be smart enough to design a CPU.
The only advantage I have right now is that I know almost nothing!
.... not poisoned by the "rules", AKA... sanity!

Time will tell.

Brad

Best of luck on this Brad - although something tells me luck has little to do with the success of your projects! I'll be following along with a lot of interest.

Cheers,
Drass.

_________________
C74-6502 Website: https://c74project.com

Thanks!
So far I have not had any issues with my circuit. Of course, at this point it's only ink and paper, so that has a lot to do with it!
I will post some sketches soon, which so far include...

20 Bit Program Counter.
Jump Control, which handles direct Jump, Return Jump, and 20 Bit Branching.
Compare Control, which drives 3 states to the Jump Control (< / > / = / => / <=).
Register Memory, which handles IO to and from the 64K General Register Memory.
Math Memory and control for the IO of the multi-function 16 bit math Module.
A single Working Register for doing certain functions like compare of two RegMem vals.

All commands (Instruction, Operand1, Operand2, Operand3) are 32 bits, and execute in a single cycle.
The Working Register is not as much of a bottle neck as it is on 6502 or PIC, and only used for a few things.

For instance, single cycle command like a direct compare against the RegMem would be : COM RMEM.LO,RMEM.HI,VAL (Result in Compare Reg).
Multiplying RegMem to a value direct would be : MUL RMEM.LO,RMEM.HI,VAL (results in MATH.LO, MATH.HI Registers).

But to add to RegMem locations together, I had to include a working register due to the RegMem requiring 16 bit addressing.
So that command would take 2 cycles, and happen like this...
LWR RMEM.LO,RMEM.HI (Load Working Register with RegMem at Address)
ADW RMEM.LO,RMRM.HI (ADD Working Register with RegMem at Address)

All math results are in a dedicated pair called MATH.LO and MATH.HI.
These values can be sent to any of the 65536 General Registers.

It will all make more sense when I show it on paper.
Basically, I am making the CPU that has everything I wanted in an AVR!...

- 1 Meg of Program Memory.
- 65536 General Working Registers.
- Single cycle 16 bit math and lookup functions.
- Jumping to any location in 1024K Program Memory.
- Branching to any location using BRNE, BREQ, BRHI, BRLO, BREH, BREL
- All Vulcan IO functionality directly integrated as instructions.

To ensure optimal single cycle performance, I am tightly controlling propagation delays into the design.
For instance, I will exploit the extra 16ns through the Instruction Decoder Matrix as a delayed toggle rather than adding a cycle.
This type of thing is predictable and worked extremely well in the design of the Video System.

I have been on the road a lot, so I have a noetpad jammed full of schematic ideas.
Next time I have an hour, I will draw out my plan into something legible and post it.

Cheers!
Radical Brad

Ok, it only makes sense to start from the foundation, and then build the mansion, so the Program Counter will be the first part of the Vulcan-74 CPU to get tested.
I have a complete plan on paper that looks like it should work, so I am starting to plug in chips.

Here is the Program Counter section of the pure 7400 Logic CPU...


Program Counter and Branch Control

As I mentioned, my CPU design will not be based on any previous designs or concepts, since I do not know enough yet!
I am going for a single cycle 32 bit speed demon that is designed for tight integration with the Vulcan Video Board.

Referring to my late night scrawl above, here is how I envision this part working...

- Program counter is a directly clocked bank of 74HC193 counters. Will shoot for 4Mhz.
- The 20 Bit Counter Address is latched through the 74HC574s to keep it a cycle behind.
- Program Memory output is 32 Bits wide for INS,OP1,OP2,OP3 on every cycle.
- The "CALL" instruction automatically captures the address before the 574s (+1) in order to "RETURN".
- There is no "JUMP", just "CALL". If you don't need to RETURN, then just don't.
- The 74HC682 and 74HC688 control the Branch / Compare logic. There is more to this not shown.
- The Compare / Branch Logic can do : BREQ, BRHI, BRLO, BREQHI, BREQLO.
- The Branch Controller also has a Timer IRQ input for a Compare Match 16 Bit timer with Prescalers.

Once again, I had more than enough parts in my bins to make this part of the CPU, so wiring shall commence soon!
For testing, an AVR will preload the Program Memory and capture the pins to do basic function testing.

After the Program Counter is up and running, I will add the 64k Register Memory and Math Memory.
So far, the complete design is not as huge as I would have figured, with perhaps 40-50 chips.
Besides the SRAMs, every single IC will be ONLY 7400 logic parts that are available from multiple sources.
In fact, the only new IC in the entire CPU so far is a 74HC682 used for compares.

Will report back when my lab is full of blue smoke!
Radical Brad

No nested CALLs I suppose then.