drogon wrote:
So overnight the little grey cells have been ticking over and I think the '816 is the way forwards for me here...BDDs only goes up to 48K RAM though, so no extra high address line latch which is what I was really looking for.
Actually, RAM in POC V1.1 is 52K ($000000-$00CFFF). I deliberately omitted the bank bits latch so I wouldn't overwhelm myself with complexity if the design had failed to work.
Below is part of the schematic for my POC V2.2 design. This is the MPU interface, which includes the hardware needed to generate the bank bits. V2.2 will have 1 MB of RAM, so address lines A16-A19 are generated.
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File comment: POC V2.2: Microprocessor Interface
poc_v2.2_MPU_interface.pdf [70.31 KiB]
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The bank bits latch is a 74ACT573. It sees an inverted clock (Ø1, identified as PHI1 on the schematic) that is derived from the clock generator flip-flop (U1, left side of page). That way I avoid the prop time penalty of an inverter in clocking the bank latch's
LE input.
This schematic also includes a data bus transceiver, which is really being used as a level converter. However, it also assures the data bus is vacated by other devices in the system during Ø2 low. Along with that, this schematic illustrates how to generate read/write signals for silicon that has separate
/RD and
/WD control inputs.
Quote:
Daryl is using a CPLD in his design, so I was really just looking for some alternatives and 128KB+ I've seen the data sheet latch arrangement and will look to replicate that in a GAL - my concern is the mention above of needing a delay, presumably delaying the latching of the data bus after Ph2 goes low, at higher speeds. We'll see.
No delay is needed in latching if you use sufficiently fast silicon, which is where the 74ACT573 gets into the picture. It's worst-case response to the
LE input is 11ns. By the time the MPU switches the data bus from bank bits mode to data mode the '573 will have already closed its latches and captured the bank bits.
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It seems it's becoming harder and harder now to build a retro style computer though - through hole stuff is becoming scarcer and scarcer, best make it now while I can!
Both Digi-Key and Mouser have plenty of through-hole logic in stock. However, big SRAMs are only available in SMT. You can get a 512KB, 5 volt SRAM in SOJ36, which can be manually soldered.
BTW, you may have noticed that I did not use any 65xx I/O silicon in my designs. I didn't have a need for the 65C22 when I designed POC V1 (still don't), and the 65C51 is defective and grossly inferior to modern UARTs.