@Garth.

The 0V line is where the blue arrow is on the lower left side 0V the image. There is no offset. The driving chip is a 74LS04 in all cases.

The resistors were placed between the output and ground of the driving chip as I was trying to increase loading..

OV low was achieved with the CMOS loads. ~0.05V for the LS TTL loads and ~0.15V for the TTL loads. I checked this with two scopes and they agreed. However I expected this as the output currents here are miniscule for the CMOS and LS TTL loads WRT to the 12mA or 24mA mentioned in the data sheets for LS TTL outputs which give typical values of 0.25V and 0.35V respectively. The 6 TTL loads might have been as high as 9mA or so.

I don't have any 74FCT, sorry.

I can certainly try some pull-up resistors but LS TTL is not really my end goal. My end goal would be testing CMOS memory and PLD devices driving CMOS loads to see if we should take the data sheet TTL environment specs seriously anymore. My concern at this time is that weird dip, which I do not get with CMOS doing the driving BTW. It only happens with the LS TTL.

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Bill

Here are some pictures of my set-up. I hope the probing one is satisfactory. It's tough to hold the camera and the probe at the same time so that shot was a bit of a nightmare.

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Bill

Thanks for the photos! Just a very quick thought - is that electrolytic certainly the right way around? I'm not sure what the effect would be if it wasn't.

Yes, ground is the lower power rail in that photo.

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Bill

Can you arrange your probing to take the ground reference from a pin of the same chip you're looking at the signal from? And if you do that, any difference between checking the driving chip versus checking a receiving chip? (Again, in both cases, using the chip's own ground pin as probe ground.)

I've done that. It's a bit of a stretch for the whisker but it's doable. It provides exactly the same results though, at least nothing I can see on the scope. The point I'm using in that picture is only an inch away from the load ground along a fairly beefy trace.

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Bill

I'm still wondering if that dip is "real" - by which I suppose I mean does a receiving chip see the dip. If it did, and if it were a clock or a strobe, that would be bad news.

It is what I'm thinking too. In the original solderless breadboard circuit the sip was a lot worse. This circuit improved it substantially - less than half as much. Also with the original circuit my other scope (a better one, but harder to get pictures off) showed the dip and it seemed almost as bad, but now with the improved circuit the better scope (UNI-T), while still showing the dip, it s only about 1/3 of what I see on the Hantek scope. I wish I had my Tektronix 475 back.

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Bill

Just a thought, again: if you double up on the bypass caps, leaving everything else as it is, does that improve matters?

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

This is typical TTL LS characteristics from page 1-52 of 1988 TTL Logic Data book. TI's characteristics seems to suggest better Voh and Vol drive capabilities than Harris.
Bill

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I went ahead and calculated the apparent internal resistance of Garth's 74LS04. Since it's a TTL chip I did not expect a single value like I would with CMOS, but I did not expect this!

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Bill

I had a bit of "enjoyment" time in the lab instead off all the cleaning up and re-arranging things today and got a couple of projects pieces done. One thing I mentioned was as above. I finally got that scope image off the UNI-T. Now we can see it side by side with the one from the Hantek.

Both these traces were taken with exactly the same experimental set-up. You can see how the "dip" is hugely reduced on the UNI-T scope. This lends a whole lot more credence to it being a measurement artifact.

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Bill

Having just acquired a 500MHz scope and probes I wanted re-visit this to see if the anomalous rising edge was still there.

Lo and Behold


It is still there. At this point I'm pretty sure that it is not an instrumentation problem.

This picture was of a 74LS04 output driving the 6 inputs of a 74ACT04

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Bill