BigDumbDinosaur wrote:
You, sir, are commended for your powers of observation. 
Well..... I have a reason for following along the design closely:
Attachment:
File comment: POC2 and a bit
board under test.jpg [ 129.15 KiB | Viewed 1112 times ]
The lower 2/3 of the board is basically the POC2, the upper third has all the I/O from a recent Z180 build. Left to right Wiz810s Ethernet header, 82C55 & IDE header, 2 chip VGA Video solution, and dumb keyboard port.
Ive been looking at building a 65816 board with BBC basic for a while, your clock stretching circuit solved the problem of limiting the speed to that of the slowest I/O components, the Z180 didn't have that problem as it has a build in wait state generator. The big advantage the 65816 has over the Z180, is no MMU to deal with and no restricted 64k visible at any one time memory.
The I/O from the Z180 build needs 4 I/O selects that also fits within the POC2 7 device memory map. So basically with the CPU, clock stretching, 128k ram and CPLD memory mapper, I had 70% of a POC2 anyway so I added provision for the serial connections.
There are differences of course, to make all 128k ram visible as well as 128k rom a 4 bank memory map is defined, and of course the video ram has its place in the memory map. However, in theory, if the memory mapping CPLD code were tweaked and the serial components fitted it ought to be compatible, if slower.
HC and HCT parts and a 70ns flash for rom limit it to 10mhz at the moment for developoing the basic I/O drivers. The 24mhz oscillator was a step to far without extending the wait stating to the rom.
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The board is electrically correct but the footprint I used for the 'AC245 transceiver was wrong. It has the right number of lands but is the wrong package width. Below is the incorrect PCB layout. The mistake is with U4, which is located at the southwest corner of the 65C816 socket.
