BigDumbDinosaur wrote:
The NXP 28L92 I am currently using in POC V1.1 can be configured for either an Intel or Motorola bus interface. Ironically, the Intel interface proved to be less a hassle to adapt to the 65C816.
For anyone who's wondering, "Motorola bus interface" could mean two things, both distinct from the Intel approach. The Motorola 68
00 bus matches that of the 6502, but the Motorola 68
000 bus is something else entirely. I remember getting momentarily tripped up by this ambiguity, perhaps in a datasheet from NXP; I don't recall.
BigDumbDinosaur wrote:
your baud rate clock should be either 1.8432 MHz or 18.432 MHz
[Edit:] Integer multiples of the exact rate do eliminate error, but 10X 1.8432 MHz isn't the only option -- you can go 3X or 5X the 1.8432 MHz, for example, and still have zero error.
BTW and FWIW, the SC16IS750 I'm playing with accepts rates up to 80 MHz on its 16X input clock. At that rate you get pretty fine resolution, so even if the math won't allow you to get your exact desired rate, you're bound to have an error that's darn small. A degree of error is tolerable anyway, as Garth noted. But running a higher input clock lets you do slightly better, FWIW.
srowe wrote:
Latching /ADS from /IO2 and Φ2 ORed together gives me reliable register reads.
I don't find your meaning clear, I'm afraid. Any chance you can post an up dated schematic, please?
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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