Looks like the little icon to the left of the "Posted:" timestamp in the top right of the post is a direct like to the post in precisely this style.

Perfect. Thanks!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Have you had any trouble with legs breaking off when you "straighten" them? They always seem to be pretty fragile.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

If you are running the 65C816 none of that is necessary, as the MVN and MVP instructions will copy up to 64KB from anywhere to anywhere. You can also use MVN as a very fast block fill instruction, such as for clearing storage, initializing a bitmap, etc. Disregarding the time consumed in servicing interrupts (MVN and MVP are interruptible instructions), the '816 can copy/fill at the rate of seven clock cycles per byte, much faster than can be accomplished with conventional load/store code.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

My first effort at a 4Mx8 SRAM module was to straighten out the SOJ pins like a DIP's pins and stack them, as shown below. I was careful of course but sensed no tendency for them to break. (This one had a '138 stuck on the end.)







The module I actually ended up with takes even less board space.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Does the wide metal strip which goes length ways over the entire stack function as the common ground?

My next project is still going to be a 65C02, but the project after that will probably be a 65C816.

Yes, it's adhesive-backed copper ribbon I got a roll of at a swap meet many years ago, cheap, that I use to hold the ground inductance to a minimum. It's not for shielding. I also put it down the length of solder-type breadboards like this one,

down the middle, on the solder side, between the ICs' rows of pins, since that area is usually empty, to give them a shorter connection to ground than they would get by going out the the strip at the edge, and to give them a lower inductance in the ground connection between ICs even at opposite ends of the breadboard, if it's a kind of circuit where it would matter.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Cool - many thanks. The one I'm doing at the moment is going to need to be pin compatible with the HY62256 so achoring that particular one can't be done that way easily (the pins don't align for the most part). This isud eot needing to into my exsting project, but future ones can obviosuly be put in the way you say.
It does look a bit fiddly, though. Mostly due to how small the ICs are.

I thought it might be something like that (rather than for shielding) - definitely a good idea. I'll have to have a mooch around Farnell or Mouser to see if they have any.

Sorry for unexpectedly bumping in: I just noticed an old posting about PHI2 and WDC parts
when following Jeff's link in the Newbie's section of the forum:


To be more precisely:

In the datasheets of most of the 6502 manufacturers, bus timing is specified relative to PHI20,
the PHI2 clock output of the CPU.

Maybe the delay from PHI0I to PHI1O and PHI2 is mentioned, maybe not...
For instance, the Rockwell R65C02 datasheet, page 12:
http://archive.6502.org/datasheets/rockwell_r65c00_microprocessors.pdf



;---

Now to take a look at a W65C02 datasheet from WDC, year 2000, page 25:
http://archive.6502.org/datasheets/wdc_w65c02s_mar_2000.pdf
In this datasheet, the bus timing is relative to "PHI0I", the clock input of the CPU,
which went renamed to PHI2 by WDC somehow...



BTW: the datasheet from 2000 says max. 22ns propagation delay from clock input to clock outputs,
in the W65C02S datasheet from 2013 this little remark about the delay is missing on page 26.
http://archive.6502.org/datasheets/wdc_w65c02s_may_17_2013.pdf

At 20MHz, 22ns would be nearly half a clock cycle.

;---

Conclusion:

For non_WDC CPUs, use the PHI2O output.
For WDC CPUs, you better stick with the clock input to avoid trouble.

Depending on the chip manufacturer, "PHI2" ain't always 'PHI2'.

I just stumbled on this thread. I'm not sure you fully understand the
concept of a starred ground.
It will not speed things up. It is intended to isolate ground currents.
In digital, you need to keep grounds clumped together, not isolate
them.
Dwight

Could you add a little quoted text Dwight? I have no idea whose post or which statement you're addressing. Thanks!

I think Dwight talks about this sentence (see below) from the first post in the thread:
And yes, I don't see how a star ground can help with speed issues either..

Sorry, it was from the first post. I hadn't noticed how far things had gone through several
pages.
I was noticing the soldering on the SOIC part earlier.
I attach a wire to each pin and then use hot glue as a strain relief.
I find that I need to put a code on each wire with a point sharpie.
A narrow band for 0 and wide for a one, to make a binary number.
I'm using a 28C64.
The next will be a PC board if I can figure out KiCad. The beginner help
could use a little help.
Dwight