Thanks for the comments Garth!

Well not sure if I want to do DMA yet. heres an updated dwg.

With Inverted Clock on 573. I bet its wrong still...

An even better choice than the HC138 is the AC138 or the F138. These two have lower prop time than the HC138.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I was going to look it over but it is in color. As I am blue-green color blind, parts of the drawing are almost invisible to me. Can you please repost it in monochrome?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Okay Updated with monocrome ,
Thanks again Garth, I was a bit confused as to which wire went where, but I suppose it does not matter. I guess I spend a lot of time thinking of the logic in my head and end up over complicating things, hence a zillion logic gates sprinkled all over the place.

Updated DWG

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

okay now for some eeprom magic, the 816 pulls a reset vector from 00FFFC and 00FFFD which is in the first 64K block, now if I put a 64K eeprom in 0 to 65535 (FFFF) then whats the memory going to do because I have 4 4Meg static ram chips. use an inverted VDP on the 138?
Something like this? SCM

would I want to put a small eprom with the reset vector address that points outside of the first 64K where the full eprom would contain the software?

I still havent figured how to get around not having a 4068 for a line for lower memory locations.
for instance. CE=A13,A14,A15 & !A16-23 which would give me a CE line for an eprom for all memory locations above 32K IE reset vector.

Many Thanks again.

Kent

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Of course Im interested. If they are smaller than the 40 Pin DIP Hitachi 4M (512Kx8) chips I am planning on using hell YA!,
I came to the same problem there are higher density chips but they are all 3.3v which was sortof a bummer.
by the way, I dont know if its going to be cost effective to try to use straight logic circuits to do the same thing as what the old PLA did in the C64, The total lag time seems to be too much of a clock killer to be a reality. I did find a very nice solution
FPGA PLA and it might just do the trick as the claims are up to 100mhz bus speed, Plus since the original 6510 had those weird pins for the tape deck being an FPGA I think I can fiddle with it to fit the 816 processor better.
still dont know if I can put the VIC II IC in this design, will have to think about that because the bus is shared between the CPU and the VIC, IE one clock is CPU the next is VIC.

What's the purpose of IC5? It seems as though all it is doing is gating the address bus, which appears to be an unnecessary function in this circuit. Since IC5 is tri-stated when Ø2 is low, you're losing the address setup time during the part of Ø2 low when A0-A15 become valid. If it were me, I'd remove IC5 entirely. Is there some alternate purpose it is serving that I am not seeing?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

If you have ROM in the first 64K of address space what do you plan to do about zero page and a stack? At reset, the '816 sets the stack pointer to $01FF and the direct (zero) page pointer to $0000. You can't move the stack until the '816 is in native mode, and even then, both the stack and page zero must remain in the lowest 64K address range. Not going to be possible if ROM is in that area.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Never mind. Evidently I hadn't gulped enough coffee when I was looking at the schematic. BTW, you should consider changing that '573 to 74ABT technology. What you have right now isn't fast enough to get the bank address latched if the clock speed is more than about 4-6 MHz.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Now that I've supercharged myself with caffeine and can more-or-less think straight, a couple of design notes:

1) Unused inputs on the MPU should not be allowed to float, as doing so makes them susceptible to noise, possibly causing strange effects that will drive you nuts. You should tie these signals to Vcc with pullups—3.3K is a good value, preferably by using SIPs, not discrete resistors. Keep the physical path between the SIPs and MPU as short as possible.

2) I said this elsewhere, but all glue logic should be (in order of preference) 74ABT, 74F or 74AC. I recommend you use a 74F138 for IC10 and IC12. Also, use a 74ABT573 at IC5. The latter has approximately 30 percent of Ø2 low in which to react to and latch the bank address. You need all the speed you can get, since that setup time is additive to the setup time on the SRAM and the prop time of the chip select logic.

3) I don't see any connections to the "G" inputs on IC12. How do you intend to have the '138 assert /Y7 when the ROM is supposed to be mapped in?

4) I believe you can eliminate IC7C by changing the manner in which you are gating IC10. The '138 is relatively slow (lots of internal gates) and adding an inverter to one of IC10's inputs adds yet more prop time to a circuit who expeditious operation is essential to being able to ramp up the clock rate.

5) You are not qualifying RWB with Ø2, which opens the door to random data corruption in SRAM due to inadvertent timing violations. D0-D7 are valid only when Ø2 is high. Otherwise, D0-D7 are either undefined (early part of Ø2 low) or hold the bank address (latter part of Ø2 low). Therefore, the /WE inputs on the SRAM should never be asserted while Ø2 is low. Carefully peruse the '816 timing diagram so this relationship is clear.

6) Is has long been customary in digital electronics notation to refer to the positive side of the power supply as Vcc and the negative side as Gnd (ground). This was an old military standard that was intended to be unambiguous. Notation such as Vss and Vdd are confusing to most of us old dinosaurs. Which one is positive?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

When looking at NMOS or CMOS parts, Vss and Vdd are more customary. Vss is the source voltage for an n-channel transistor, which makes it GND. Vdd is the drain, thus making it +Vcc in the TTL world.

"Which one is positive?" was a rhetorical question. Outside of the distinctions of NMOS or CMOS hardware, the Vdd and Vss designations are too close to each other to be unambiguous.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!