Here's your diagram again, but modified to take Phase 2 out of the RBA14 signal. I'm not terribly surprised you were able to make the old version work, but it does "break the rules", and is asking for trouble. From the SRAM's point of view, all addresses should be stable before CE goes true.


Just be sure that when the Bank Select bits get altered, the program that does the alteration doesn't reside in the area being remapped. In other words, don't pull the rug out from under your own feet!

-- Jeff

How much of a n00b am I? Thanks for your help! I'll update my progress on the PWA thread.

-EyE

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65Org16:https://github.com/ElEctric-EyE/verilog-6502