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PostPosted: Wed Mar 06, 2013 3:01 am 
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BigDumbDinosaur wrote:
Also missing were the 65C816's VDA and VPA address bus qualification outputs. Their omission strongly suggested that something had to have been done to prevent the false address bus states that the '816 generates during certain stages of some instructions, especially those with <addr>,X and <addr>,Y addressing.
Interesting point, well worth mentioning. Still, do we conclude that "something had to have been done," or, "it would have been nice if something had been done"?

If the '816 and '802 are the same basic die, differing only in some of the metalization, it doesn't seem plausible that invalid-address cycles would appear (as we know they do) on the '816 but not on the '802. What seems more likely to me is that the '802 also exhibits the invalid-address cycles, and, since VPA and VDA outputs are absent, this is a hazard with no good solution. IOW, people using the '802 would need to be on guard against the possibility that an invalid address would read from an IO device, which, on some devices, can erroneously alter status.

Odd (and disappointing) as this seems, it doesn't contradict the definition of the '802 as a drop-in replacement for an NMOS 6502, since the latter exhibits the same hazardous behavior. (Or was the '802 touted as a drop-in replacement for the 'C02 as well?)

cheers,
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PostPosted: Thu Mar 07, 2013 2:18 am 
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Dr Jefyll wrote:
BigDumbDinosaur wrote:
Also missing were the 65C816's VDA and VPA address bus qualification outputs. Their omission strongly suggested that something had to have been done to prevent the false address bus states that the '816 generates during certain stages of some instructions, especially those with <addr>,X and <addr>,Y addressing.
Interesting point, well worth mentioning. Still, do we conclude that "something had to have been done," or, "it would have been nice if something had been done"?

If the '816 and '802 are the same basic die, differing only in some of the metalization, it doesn't seem plausible that invalid-address cycles would appear (as we know they do) on the '816 but not on the '802. What seems more likely to me is that the '802 also exhibits the invalid-address cycles, and, since VPA and VDA outputs are absent, this is a hazard with no good solution. IOW, people using the '802 would need to be on guard against the possibility that an invalid address would read from an IO device, which, on some devices, can erroneously alter status.

Odd (and disappointing) as this seems, it doesn't contradict the definition of the '802 as a drop-in replacement for an NMOS 6502, since the latter exhibits the same hazardous behavior. (Or was the '802 touted as a drop-in replacement for the 'C02 as well?)



Back in the mid 80's I did swap the 65c02 in an apple IIe for the 802 and it worked fine. The Merlin 8/16 assembler I used at that time had an option that would actually use the 802 instructions to enhance Merlin's performance.


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PostPosted: Thu Mar 07, 2013 5:19 am 
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Dr Jefyll wrote:
BigDumbDinosaur wrote:
Also missing were the 65C816's VDA and VPA address bus qualification outputs. Their omission strongly suggested that something had to have been done to prevent the false address bus states that the '816 generates during certain stages of some instructions, especially those with <addr>,X and <addr>,Y addressing.
Interesting point, well worth mentioning. Still, do we conclude that "something had to have been done," or, "it would have been nice if something had been done"?

If the '816 and '802 are the same basic die, differing only in some of the metalization, it doesn't seem plausible that invalid-address cycles would appear (as we know they do) on the '816 but not on the '802. What seems more likely to me is that the '802 also exhibits the invalid-address cycles, and, since VPA and VDA outputs are absent, this is a hazard with no good solution. IOW, people using the '802 would need to be on guard against the possibility that an invalid address would read from an IO device, which, on some devices, can erroneously alter status.

Odd (and disappointing) as this seems, it doesn't contradict the definition of the '802 as a drop-in replacement for an NMOS 6502, since the latter exhibits the same hazardous behavior. (Or was the '802 touted as a drop-in replacement for the 'C02 as well?)


Maybe the '802 uses the same trick that the 'C02 uses (do another opcode fetch instead of invalid address read). What does the '816 do during those cycles ?

Edit: to answer my own question, I tried it out, and the '816 does generate an invalid address cycle for abs,X (but with VDA not asserted, of course). Still, since they had the logic for the 'C02, it is plausible that they have a metal option to switch between the 'C02 and the '816 behavior.


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PostPosted: Thu Mar 07, 2013 6:38 am 
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Arlet wrote:
Maybe the '802 uses the same trick that the 'C02 uses (do another opcode fetch instead of invalid address read). What does the '816 do during those cycles ?

Edit: to answer my own question, I tried it out, and the '816 does generate an invalid address cycle for abs,X (but with VDA not asserted, of course). Still, since they had the logic for the 'C02, it is plausible that they have a metal option to switch between the 'C02 and the '816 behavior.

Unless someone has a 65C802 and a circuit in which it can be tested to see what happens with instructions that generate false address bus states in the 65C816 this will most likely remain a mystery.

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PostPosted: Thu Mar 07, 2013 7:22 am 
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Quote:
Edit: to answer my own question, I tried it out, and the '816 does generate an invalid address cycle for abs,X (but with VDA not asserted, of course). Still, since they had the logic for the 'C02, it is plausible that they have a metal option to switch between the 'C02 and the '816 behavior.

Can you confirm for us what the invalid address read was. They were not random, but quite predictable—just invalid. If I'm correctly understanding the article in the Dec '83 issue of Byte magazine, "The CMOS 6502," p.446 says the problem with the NMOS one was that indexing across a page boundary would add a cycle for the carry, and the first read, which is the invalid one done during the correction of the page number, is of the target address minus $100; and if it reads an I/O IC and thus changes some status, there's a problem. Well, this assumes you have a table in RAM or ROM that starts in the same page with the I/O. I expect that would be extremely rare, for example to have I/O from $6000-$607F, then RAM or ROM starting at $6080 and extending into (and probably beyond) page $61. I use an '802 all the time, and in over 15 years of doing so, have never had this problem. However, I also don't have I/O and memory in the same page.

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Unless someone has a 65C802 and a circuit in which it can be tested to see what happens with instructions that generate false address bus states in the 65C816 this will most likely remain a mystery.

It seems like I need to make a list of things to try when I get a chance to get the fixture out again and do some single-cycling to check things like this.

BDD, can you give us the link to the post again where you described the problem you had before implementing the VDA and VPA signals.

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PostPosted: Thu Mar 07, 2013 9:06 am 
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GARTHWILSON wrote:
Quote:
Edit: to answer my own question, I tried it out, and the '816 does generate an invalid address cycle for abs,X (but with VDA not asserted, of course). Still, since they had the logic for the 'C02, it is plausible that they have a metal option to switch between the 'C02 and the '816 behavior.

Can you confirm for us what the invalid address read was. They were not random, but quite predictable-- just invalid. If I'm correctly understanding the article in the Dec '83 issue of Byte magazine, "The CMOS 6502," p.446 says the problem with the NMOS one was that indexing across a page boundary would add a cycle for the carry, and the first read, which is the invalid one done during the correction of the page number, is of the target address minus $100; and if it reads an I/O IC and thus changes some status, there's a problem.

The '816 has the same behavior as the NMOS 6502. First, it has a cycle with the address minus the carry in the upper byte, then follows a cycle with the correct address. Here's what I see on the address/data bus. I have X=$F8, and I do LDA abs, X from $206, $207, $208, $209:
Code:
f015 bd (LDA $206, X)
f016 06
f017 02
02fe 00 (read from $2FE)
f018 bd (LDA $207, X)
f019 07
f01a 02
02ff 00 (read from $2FF)
f01b bd (LDA $208, X)
f01c 08
f01d 02
0200 00 (invalid read from $200)
0300 00 (read from $300)
f01e bd (LDA $209, X)
f01f 09
f020 02
0201 00 (invalid read from $201)
0301 00 (read from $301)


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PostPosted: Thu Mar 07, 2013 7:06 pm 
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I did some additional test on my 65816, with a read, a write and read-modify-write instructions, and I also captured some extra control signals. Here's the code:
Code:
F006  BD 07 02        lda   $0207, x   ;
F009  BD 08 02        lda   $0208, x   ;
F00C  9D 09 02        sta   $0209, x   ;
F00F  FE 0A 02        inc   $020a, x   ;

And here's the trace. Again X = $F8.
Code:
Addr Data (Reset, VPA, Vector pull, Write, VDA)
f006 bd .P..D (LDA $0207, X)
f007 07 .P...
f008 02 .P...
02ff 00 ....D

f009 bd .P..D (LDA $0208, X)
f00a 08 .P...
f00b 02 .P...
0200 00 .....
0300 00 ....D

f00c 9d .P..D (STA $0209, X)
f00d 09 .P...
f00e 02 .P...
0201 00 .....
0301 00 ...WD

f00f fe .P..D (INC $020A, X)
f010 0a .P...
f011 02 .P...
0202 00 ..... (read from invalid address, with VDA not asserted)
0302 00 ....D (read from valid address, now with VDA asserted)
0302 00 ...W. (write cycle with invalid data, VDA not asserted)
0302 01 ...WD (good write cycle with VDA asserted)


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PostPosted: Fri Mar 08, 2013 1:30 am 
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Arlet wrote:
The '816 has the same behavior as the NMOS 6502.
This is as I already stated several posts ago, here. "The [NMOS 6502] exhibits the same hazardous behavior."

I think the waters got murky when, in the immediately following post, clockpulse reported no difficulty after replacing a 'C02 with an '802. But his success is not at odds with the content of my post, and I apologize for not clarifying at this point. He had no difficulty because read-sensitive IO devices were not present and/or because of the factors Garth mentioned -- ie; that the code and the device mapping have to be "just so" in order for the invalid addresses to actually result in a problem. Were the problem more prevalent, the NMOS 6502 would not have been a success.

Arlet wrote:
to answer my own question, I tried it out, and the '816 does generate an invalid address cycle for abs,X
It's always nice to get the info straight from the horse's mouth! :D But for those of us who don't have test gear and an '816 system handy, just refer to Table 5-7 of the '816 Data Sheet. There's a 7-page listing of what the '816 does on every cycle of every instruction. Far fom being mysterious, the invalid address states are, as Garth says, quite predictable.

cheers,
Jeff

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PostPosted: Fri Mar 08, 2013 3:16 am 
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GARTHWILSON wrote:
BDD, can you give us the link to the post again where you described the problem you had before implementing the VDA and VPA signals.

The forum discussion starts here. I also mention it on my POC website.

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PostPosted: Fri Mar 08, 2013 3:20 am 
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Dr Jefyll wrote:
It's always nice to get the info straight from the horse's mouth! :D But for those of us who don't have test gear and an '816 system handy, just refer to Table 5-7 of the '816 Data Sheet. There's a 7-page listing of what the '816 does on every cycle of every instruction. Far fom being mysterious, the invalid address states are, as Garth says, quite predictable.

Hence the presence of the VDA and VPA qualification outputs.

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PostPosted: Fri Mar 08, 2013 5:32 am 
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BigDumbDinosaur wrote:
GARTHWILSON wrote:
BDD, can you give us the link to the post again where you described the problem you had before implementing the VDA and VPA signals.

The forum discussion starts here. I also mention it on my POC website.

So now after having re-read many pages, I still don't see what addresses were hitting the DUART. It appears to reside at D100-D1FF, but I thought the forum topic was saying that the processor was reading D000 and then writing to the final valid address in the DUART in the next cycle. D000 does not enable the DUART though, so there would not be two DUART accesses in two consecutive cycles. What was getting read in that invalid address?

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PostPosted: Fri Mar 08, 2013 6:12 am 
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GARTHWILSON wrote:
So now after having re-read many pages, I still don't see what addresses were hitting the DUART. It appears to reside at D100-D1FF, but I thought the forum topic was saying that the processor was reading D000 and then writing to the final valid address in the DUART in the next cycle. D000 does not enable the DUART though, so there would not be two DUART accesses in two consecutive cycles. What was getting read in that invalid address?

The DUART is at $00D100—there were some typos on my webpage that seemed to make the DUART appear at $00D000. Dunno if these errors propagated to the forum.

I am using <addr>,X addressing to select a DUART specific register and from what I was able to determine, the STA $00D100,X instruction being used to write to the channel command register was actually hitting $00D100 on cycle four, followed by the correct address ($00D100+$02 or $00D100+$0A) on the final (fifth) cycle. That constituted two consecutive accesses spaced by only one Ø2 cycle, which violated the device's timing requirements when the command registers were involved. Qualifying all memory cycles with VDA and VPA prevented the DUART's /CS from being asserted on the fourth cycle, thus fixing the problem.

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PostPosted: Fri Mar 08, 2013 6:22 am 
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Of course-- D100 is the bottom of the page, so I don't know why I was thinking of D000. Too many distractions. :oops:

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PostPosted: Fri Mar 08, 2013 8:14 am 
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Dr Jefyll wrote:
I think the waters got murky when, in the immediately following post, clockpulse reported no difficulty after replacing a 'C02 with an '802. But his success is not at odds with the content of my post, and I apologize for not clarifying at this point.

I got your point, but I think there's still two possibilities: the '802 has the same problems as the NMOS 6502, or the '802 design inherits the 'C02 workarounds for the invalid accesses. The fact that there's only metal changes between the '802 and '816 does not necessarily imply that their behaviour in this regard needs to be the same.

The WDC programmer's manual comes close to making a verdict here:
Quote:
Both have a 6502 emulation mode, in which the 6502’s register set and instruction timings emulate the eight-bit 6502 (not the 65C02) exactly (except they correct a few 6502 bugs).

Saying that the '802 resembles the NMOS 6502, rather than the 'C02. However, it still leaves open the possibility that the invalid address cycles are considered 'bugs', and therefore have been corrected. The manual also says:
Quote:
Remember that even as the 65C02 is a superset of the 6502, the 65802 and 65816, described in the next chapter, are supersets of the 65C02. All of the enhancements found in the 65C02 are additionally significant in that they are intermediate to the full 65816 architecture.


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PostPosted: Fri Mar 08, 2013 10:26 pm 
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Arlet wrote:
The WDC programmer's manual comes close to making a verdict here:
Quote:
Both have a 6502 emulation mode, in which the 6502’s register set and instruction timings emulate the eight-bit 6502 (not the 65C02) exactly (except they correct a few 6502 bugs).

Except the 65C816 data sheet contradicts the above statement. The false address bus cycles exist in either mode, which I realized when I first ran into the issue. At that time, POC V1 was operating the MPU in emulation mode. Clearly the timings aren't (can't be) the same as the NMOS MPU, which the '816 timing diagram illustrates.

Quote:
The manual also says:
Quote:
Remember that even as the 65C02 is a superset of the 6502, the 65802 and 65816, described in the next chapter, are supersets of the 65C02. All of the enhancements found in the 65C02 are additionally significant in that they are intermediate to the full 65816 architecture.

The Eyes and Lichty manual has a number of errors, which mostly exist because that tome was written in the 1980s and never updated to reflect WDC enhancements that were subsequently made (which I believe coincided with the conversion of the 65C02 and 65C816 to static cores). For example, the manual states that the BBR, BBS, RMB and SMB instructions were unique to the Rockwell version of the 65C02, which they aren't—these instructions are present in the W65C02S. The manual also implies that the 65C816 and 65C802 are exactly a 65C02 when operating in emulation mode, which isn't the case. BBR, BBS, RMB and SMB do not exist in the 65C816 in either mode, the B-accumulator is always accessible, and so are the data and program bank registers (but of very limited value). 65C816 instruction timings are the same in either mode as well when acting on eight bit values. It's also important to note this caveat from the 65C816's data sheet:

Quote:
7.8 All Opcodes Function in All Modes of Operation
7.7.1 It should be noted that all opcodes function in all modes of operation. [emphasis added] However, some
instructions and addressing modes are intended for W65C816S 24-bit addressing, and are therefore less
useful for the emulation mode. The JSL, RTL, JMP al and JML instructions and addressing modes are
primarily intended for W65C816S native mode use.
7.7.2 The following instructions may be used with the emulation mode even though a Bank
Address is not multiplexed on the Data Bus: PHK, PHB and PLB
7.7.3 The following instructions have "limited" use in the Emulation mode:
7.7.3.1 The REP and SEP instructions cannot modify the M and X bits when in the Emulation
mode. In this mode the M and X bits will always be high (logic 1).
7.7.3.2 When in the Emulation mode, the MVP and MVN instructions use the X and Y Index
Registers for the memory address. Also, the MVP and MVN instructions can only move data within the
memory range 0000 (Source Bank) to 00FF (Destination Bank) for the W65C816S, and 0000 to 00FF for
the emulation mode.

Unfortunately, I no longer have a 65C802 data sheet and no longer recall that MPU's details. I do seem to recall, thought, that like the 65C816, the 65C802's 'C02 emulation wasn't exact.

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