I did grapple with the AC logic at the beginning, but found that many devices are either hard to find, single sourced, or SMD only.
For this reason, I decided that the extreme power of the GPU would offset any reduction in 6502 speed (if required).
To be honest, even running the 6502 at 4MHz here (ack!), Vulcan-74 can make an Amiga look like a turtle.
This is also the reason I will not use a VIA or any other custom IC with a single source.
The 65C02 is the exception of course, since the entire goal of this project was to give it a deserving home!
Everything on the entire board with the exception of the SOJ package SRAM is only 74HC readily available DIP Logic.
Being eccentric (crazy, off-the-wall, wonky, etc), when I set rules at the beginning of a project like this, they are set in stone.
This project would have been scrapped instantly if any goal could not have been met. I am glad I am past that point now!
I am not doing all that bad with the 74HC138's so far. I have actually exploited the propagation delay through the 74HC688 that decodes the high address bits so that the IO chain (10 x 74HC138) is not "fired" until after the entire 16 bit address and 8 bits of data sent from the 6502 have stabilized. Because of this, and the fact that the next address read from the 6502 will be program memory, RW is not needed in the equation. After toggling an IO, the following program memory read flips the bit back up as the 688 comparator lets go.
With an IO read cycle hold-back hack, I expect to reach between 16MHz and 20MHz using only HC logic.
If this fails, I will register the output with a 74HC574, and allow it to propagate as the 6502 chews on the next program memory read....
6502 : "Hey Vulcan, here is an IO request, but I don't think you can fulfill it before my next read cycle"
Vulcan : "Dude, don't worry about me, you just keep on readin' and I will be ready next time you need me"!
6502 : "OK Bro, here it is; trip the Page Flip Bit at address 567, and swap out those video buffers".
I will show this in more detail soon, with some schematics and videos to back up my outlandish claims!
Ps,
I have been enjoying your projects Dino... great source of inspiration and information!
Keep it coming!
Cheers!
Radical BradBigDumbDinosaur wrote:
Oneironaut wrote:
Where I may have issues beyond 10MHz is the reading of registers on the Vulcan Video Board. My IO system decodes IO lines at address 512, using a series of 74HC138's triggered by a 74HC688.
Perhaps this would be the time to consider making a switch from 74HC to 74AC logic. Dunno if that is in keeping with the ground rules you set for this project, but if it is, you will substantially reduce prop delays through your gates, especially the 74HC138s, which are inherently slow devices.
Also, as a reminder, the most recent version of the Kowalski simulator can be gotten at
http://www.exifpro.com/downloads/6502_1.2.12.zip.