As I mentioned in my
POC V2 topic, I've concocted a way to add SCSI (specifically, single-ended SCSI-2) to my POC unit. POC V2 will include on-board SCSI, along with CPLD glue logic, but I though it best to do the SCSI development work within the realm of something that already functions and is stable. By adding SCSI to POC V1, I'm not faced with debugging a whole new design if something doesn't work right. Also, V1 has a fully functional M/L monitor and a Motorola S-record loader in ROM, so I can develop a driver on my UNIX box and then ship it to the POC unit for testing.
A while back, I acquired some 53C94 SCSI controllers, around which I've designed a plug-in host adapter. The 53C94 offloads all of the SCSI bus protocol steps from the host processor, greatly simplifying the circuit design, as well as the code required to drive the bus and talk to SCSI devices. The 53C94 requires little in the way of supporting silicon. The controller is capable of directly driving the SCSI bus, eliminating the need for line drivers, unless a high voltage differential bus is desired. A TTL or CMOS clock source running between 10 MHz and 25 MHz is required to generate the internal timing signals used by the 53C94's state machine. In theory, that clock could be derived from the Ø2 clock on the POC board. However, the configuration of several registers in the 53C94 is contingent on the clock rate, which I may change in the course of experimentation. I don't want to have to burn a new EPROM each time I fiddle with Ø2, so I'll use a separate clock generator (20 MHz, in this case) on the HA.
The 53C94 is capable of synchronous SCSI bus transfers at the rate of 10 MB/second. However, that mode of operation isn't practical with the 65C816 without a DMA controller. Synchronous operation increases throughput by not handshaking each byte on the bus, which implies that the host system must be able to read or write the bus at a rate greater than it can actually operate. As the 65C816 can't move data at SCSI-2's synchronous rate, an attempt to run in synchronous mode would likely result in data overrun during any of the data-in phases or an underrun in the target device during a data-out phase. Accordingly, I will run the bus asynchronously, which (in theory) can be done at very slow rates. For example, the Lt. Kernal subsystem for the C-128 ran at only 65 KB/second in FAST mode, a mere 2.6 percent of the base asynchronous rate supported by the SCSI-1 standard (2.5 MB/sec). My preliminary calculations suggest a maximum of 750KB/second with the '816 running at 20 MHz (not possible with POC V1). As loads and stores consume the bulk of the processing time, that rate will probably decrease almost in proportion to Ø2. Assuming this HA will function with the current Ø2 rate of 12.5 MHz, I might be able to achieve 450 KB/sec.
There is no expansion port on the POC, so I decided to use the Dallas watchdog timer's socket as a makeshift expansion port, as all but two of the signals required to control the 53C94 are already present. Several of the watchdog's socket positions are unused, so a simple patch to the POC board connects /IO-2 and RST (the missing signals) to the vacant pins. The host adapter itself mounts on three standoffs on the POC board and plugs into the watchdog's socket. The watchdog, in turn, plugs into a socket on the HA and (in theory) should be none the wiser about the change.
Owing to its intended use, the 53C94 will generate an interrupt each time the SCSI bus changes phase (the target device controls bus phases once arbitration and selection have occurred). Other events can also generate an IRQ, such as target device selection timeout. Most of the possible IRQ sources can't be disabled, which initially increases the difficulty of creating a basic driver. So I rigged up the host adapter so I can isolate the 53C94 IRQ output from the POC's IRQ circuit.
The finished driver will ultimately be a combination of foreground and interrupt-driven code. Each phase will have a code segment that fulfills whatever requirements are peculiar to that phase. There will also be segments to handle interrupts caused by events such as unexpected phase change, data transfer timeout, etc. In a general sense, the IRQ part will "dispatch" the main driver loop by changing the RTI address on the stack to point to the correct segment. This is where the 65C816's LDA n,S and STA n,S instructions will come in handy.
Anyhow, I've got the HA PCBs ordered and will post more as I progress.
SCSI-2 Host Adapter Schematic
SCSI-2 Host Adapter PCB Layout
NCR 53C94 SCSI Controller (PLCC84)
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