The same frequency. To cut it in half, you need to divide it using a flip-flop. The resistors are in the circuit for bias reasons. A TTL-family part's inputs are at a high logic level if no DC is pulling them down externally.


The RF problems come from rise time, not really the square waves' fundamental frequencies. If you build with fast parts, you need to build accordingly, even if you run them at low frequencies. Put the parts close together and keep the wire lengths short. A ground plane will be very helpful, as it drastically reduces the inductance of the ground connections and therefore the groundbounce. You can get perfboard for wire-wrap jobs with a ground plane. Going further, you can get it with planes on both sides so you can use one for Vcc also; but wiring the Vcc instead and using decoupling capacitors with short lead lengths (or even chip capacitors) from the Vcc pins to the ground plane will do the job well too. If you use the chip capacitors, you might want to get the perfboard with thru-plated holes so you can solder the pin so movement of the socket won't break the chip capacitor or its connections. The board with a plane on both sides and thru-plated holes however can get pretty expensive and is probably not necessary.


I wouldn't say it's an achiles heel, but it partly holds the key to why the 65xx's performance is so high for its clock rate compared to its contemporaries. Intead of taking four clocks for a read or write, it really does it in half a clock, and some computers even took advantage of this to do two memory accesses per clock so both the processor and the video could run from the same memory at the same time at full speed without waits.

The pre-packaged clock oscillator cans are dirt cheap and already have 5ns slew rates -- there is no need for any F-TTL logic to shape the waveform. You would need to use the F-TTL wave shaper logic ONLY if deriving the clock from another source (e.g., dividing down a higher-speed clock).



Put an oscilloscope on any trace and just watch what happens. You'll be amazed at the RF hash that comes out. Remember: the 65816 has *fast* transitions on its signals, so it still puts out VHF or better frequencies.

To answer your question, though, yes, Harry's circuit can handle that kind of speed (4MHz or even faster). And, yes, the clock is definitely the 65816's achillies heel. Still, it's workable as long as you're careful and pay attention to detail.

The clock is definitely the achilles' heel for the 65xx family. If the slew rate is too slow, the internal operation of the CPU becomes unstable. If the address decoders aren't gated by the clock, then you get memory corruption. Etc.

These reasons are why FPGA and other high-density logic chips use fully synchronous designs. For example, the Wishbone bus can be thought of as a 2nd-generation 65xx bus -- single-cycle reads and writes, 32-bits with individual lane strobes, etc., pickles and onions, and a side of ketchup, to go please. Yet, it does everything NOT with high-level or low-level logic. (or worse, both). Instead, everything is clocked on the rising edge of the clock. And I do mean everything. There literally is absolutely no exception to that rule.

I suppose one can say that the 6502 bus is similar, since everything is clocked on what appears to be the falling edge of phase 2. But the 65816 is a whole different beast, managing its bus with both edges, and in the case of the bank address, *levels* as well.

It is for this reason that the 65816 needs to have such a pristine clock source. Without it, it starts to malfunction in seemingly random ways.

@GARTHWILSON

Thank you for the explanation and kind advice - I'm sure I'll be needing it before long.

@kc5tja

I see. Sounds like I just need to look a bit harder for oscillators with tighter rise and fall times then.

Incidentally, I remember reading somewhere online (can't provide a link, sorry - I've been through several dozen hobby electronics websites over the past couple of weeks and it's all blurred together by now) that said that the 65816 is the most hobbyist-friendly CPU available nowadays; that's why I chose that instead of the 65C02 which is closer to the 6510 that I'm used to. Considering I'm a total n00b when it comes to electronics, would you say that the '02 or the '816 would be a better choice for "my first homebrew"?

and

The '816 is much easier to program especially if you're doing a lot with 16-bit numbers, like calculating addresses. It just has a lot more resources in the way of instructions, addressing modes, wider registers, etc.. The 65c02 will be easier hardwarewise though. (BTW, do use a 65c02, ie, CMOS, not the old NMOS 6502.) I have not used an '816 yet, just the '802 which is basically an '816 made to be dropped into a 65c02 socket and doesn't have the 16MB addressing capability. It has the same 5ns input clock spec. and I have not had any trouble. I still have to think kc5tja had another problem that made his circuit a lot less tolerant of less-than optimum rise times, and I still hope we can get that figured out. But of all the 65c02/802 computers I've made, the only one that did not work on the first try was the very first one when I didn't realize yet that the 65c22 CS inputs must not be gated by phase 2.

Of the various 65c02/802 designs I've done, I've never payed particular attention to rise time, and never had any problem. However, I have always exercised that nebulous thing we call "good engineering practice" when things get hard to model. That's a lot easier than troubleshooting after the fact. One of these designs is flying in aircraft all over the world, using only a resistor and capacitor hung on the processor to generate the clock signal. Rise and fall times on that one are on the order of hundreds of nanosecons, but there's no ringing or other noise on that input. The phase-2 output signal of my workbench computer is pretty slow because there are so many things hung on it, and I expect the maximum operation frequency could be a little higher than its 7MHz (with 4MHz and 6MHz parts) if I were to rebuild it and do the clock circuit better.

@GARTHWILSON

Thank you for the advice. Since I don't want to spend a ton of money on test equipment (at least initially), I want to keep things as simple as possible so I think I'll stick with the 65c02 for my first forays into homebrew computer design. I've spent over a decade working within the confines of the 6510's instruction set, so to me the 65c02 is already an upgrade - INC A here I come!

I'm still studying this circuit, and I think I have it 90% figured out what's going on. But I still have one small question.

Isn't the third Inverter redundant? It would appear all of the requirements are met within the circuit.

If anyone could explain this to me, that would be great!

The third inverter is used as a buffer, to isolate the oscillator from the load.

On Mon Oct 16, 2006 5:05 pm, I wrote:

I didn't look at the details. Changing the last two to
viewtopic.php?p=895
viewtopic.php?t=195
does the job. My post at the bottom of the one ending in "p=895" has links to a bunch of applications notes on comparing and interfacing the different logic families, and potential problems you can run into with the faster logic families if your construction method is not suited for them.

I put my clock circuit on a scope, and it looks pretty good. But I noticed it's only approx. 1.85 volts. When I read the data sheets for W65C02, it says that the clock input needs a minimum of 4.35 volts.

I would assume from this that my clock shouldn't run the W65C02, yet it does.

Am I missing something?

If it works, I would assume it's more than 1.85V. 1.85V doesn't even meet minimum LSTTL input levels, let alone output levels. Did the vertical voltage variable knob get out of the "CAL" position?

That's a good question, I'll have to check when I get back (I'm out of town), but I also put a multi-metre on it, and it also read 1.85 volts. When I probed the CLK out pin (39) it was a slightly better square wave, but it read 2.25 volts with the multi-metre.

Well, I double checked, and you were right. I had my setting wrong, and I'm actually reading about 4.3 volts at the peak.

I do have another question though. What causes the dip into negative when the signal falls to 0 volts, and then a kind of unstable squigile before it rises again. I assume this is some kind of imperfection in the circuit.

That's from unwanted inductance in the connections. The faster the rise and fall times output by the parts you're using, the more careful you have to be with your construction, regardless of clock speed. If it gets bad enough, things will quit working. If you're on the raggedy edge, it may seem to work fine, and then something like power supply voltage or temperature change slightly and it no longer works and it leaves you wondering what happened. The issues are explained well in the ap. notes linked at the forum topics mentioned above.