Jmstein7 wrote:
Proxy wrote:
you people, stop giving me ideas for FPGA softcores!
just imagine it, a true 16-bit 65816 with a full 24-bit Address bus and 16-bit Data bus... what a project that would be!
Well, I have a starting point for that, if you want one. It already has the data lines demultiplexed:
https://github.com/jmstein7/soft_65c816_core_SoC_23LC512All you'd have to do is demultiplex the address lines, and, voilà, Bob's your Uncle! (And Fannie's your Aunt!)
Go! Make it a reality
Jon
thanks for the offer, but that 65C816 core still seems to have an 8-bit Data bus though. (or i'm reading VHDL wrong... i'm not sure, i've only ever used Verilog)
what i meant is a true 16-bit Data Bus, like the 8086 compared to the 8088, or the 68000 compared to the 68008.
which is a lot more tedious than just hooking up an existing 65816 to an external 16-bit bus. i basically have to build it from scratch.
For example instructions that are 2 or 4 bytes long take a different amount of cycles to fetch depending on if they are located at an even or odd address.
Same with accessing 16-bit words from Memory. aligned accesses would be 1 cycle long, but unaligned would take 2 cycles.