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x86?  We ain't got no x86.  We don't NEED no stinking x86!

An easily solved problem, hardly worth mentioning a second time. Not that it should be excluded from the list of pros and cons. But we know how to deal with this.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I've updated the schematic to use the logical gates rather than the chips, and I've switched the quad-and that was slow. I've reset my EasyEDA to be black on white from white on black. Hopefully this is getting into better shape. I've also been reading the primer that was listed, lots of great info.


Happy Hollidays all,
-- Justin

There is also a 74HCT21; my JRC-1 build uses it for its IRQs. I would've preferred something faster, but I couldn't seem to find this particular part in AC or AHC logic. Fortunately a slightly slower IRQ propagation isn't gonna be a big deal.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Nice, I'll make a note of that one for future use. And it looks like the pin pitch is 0.65mm which is not a big deal to hand solder.

Justin, I have a few minor suggestions regarding your schematic (although I haven't checked it thoroughly).

The first point is actually very minor -- there's a little typo, so to speak:

In the next image (below) I've shown how to reduce the propagation delay involved in generating CE# for the ROM. The proposed change doesn't alter the memory map. And reduced prop delay is generally desirable, for example in allowing higher clock rates, if you ever decide to experiment with that.

This next mod interposes a logic gate between the oscillator and the rest of the circuit. I suggest this because oscillator outputs don't always have good voltage levels and snappy rise & fall times. That's a potential source of flakiness, given that the clock input of the CPU is somewhat fussy (according to published specs, at least).

Finally, you've used quite a large number of VIA pins to control the LCDs. That's not exactly a problem, but you might prefer to reduce that number in order to leave more VIA pins free for other purposes. It seems to me the E2 pin could be tied off (hi or lo, I'm not sure) rather than consuming a VIA pin. Also, the X9C103 digital potentiometer could have its INC and U/D pins attached to two of the PortA pins, in effect sharing those pins when they're not actively in use communicating with the LCD. Only the CS pin of the X9C103 truly needs a non-shared VIA pin. Again, this isn't exactly a problem, but you might prefer to leave more VIA pins free for other uses.
-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Jeff,

Thank you for the feedback! I'm going through each of them now.

With the change to the memory map logic, it would increase the speed of the #ROM single, but all other signals would still be slow. Currently the memory map takes (I think, if I'm reading the data sheets correctly, though I may not be)
decoder sheet and sheet
#RAM takes 40ns for the decoder
#ROM takes 40ns for the decoder and 25ns for the and
All other signals take 40ns + 40ns for the 2 decoders

Will it make a difference to speed up the #ROM signal if the others are still slow? I think I'd still be limited by the slowest signal line?

I'm not sure of a better way to note it (I have a note on the bottom of the schematic) that the 2 clocks are for 2 footprints and won't both be used at the same time. I'll see if I can move it up to near the 2 oscillators.

I'll look over the LCD connectors and data sheet and see if I can clean that up any, I may make that round two though and just keep everything separated for now.

Thanks
-- Justin

It may or may not make a difference; I'll get to that in a moment. Firstly lets notice that the proposed mod is "free" in the sense that no additional gates are required. So the improvement, if any, is "pure gravy."

It's true, as you say, that all the other Chip Select signals from the decode logic will still be slow (at least based on the prop delay in the datasheets, but these can be overly pessimistic). For this and other reasons the "critical path" that limits the computer's maximum clock frequency may not be where you expect. Remember, too, that after a Chip Select goes true you then have the access time of the device itself.

Changing to a faster RAM may change where the critical path lies. Or, having an earlier ROM Chip Select signal may allow you to get away with using a particularly slow ROM, and that option may prove useful. Or maybe later you'll upgrade some or all of the glue logic from 74HC to 74AHC, leading to a new situation. It's hard to predict what might happen in future. So, speaking for myself, if I see an easy way to make something faster I'll usually just do it. We don't need to prove there'll be a benefit -- we only need to be reasonably sure there's no downside.

Yes, I saw the note, and realize only one oscillator would be used.

Yes, there are advantages to starting with the simplest approach.

As for "round two," that could, if you wish, entail simply a wire mod to the already existing "round one" PCB. It's only a few traces you'd need to cut and patch. Something to keep in mind when you do the layout for round one. But no biggie -- it's up to you. I'm not gonna tell you how to play with your toy!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

So this is the PCB, its 82mm x 218mm in size. Any issues? I'm thinking of ordering a few this weekend.

It might be an idea to post your latest schematic revision. It's a little difficult to see it things are correct by looing at a PCB layout image like these.

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Bill

Makes sense

I probably didn't read everything, but I have some questions:

First, is this a 2-layer or a 4-layer board? I see lines running to and from those bypass capacitors, which makes me think it's a 2-layer board. BUT the traces for those (which would be VCC and GND) are really tiny, just as big as a signal trace. I personally don't know if that really changes anything, but I was told and implement myself larger traces for VCC and GND coming from capacitors.

Also, if it's a 2-layer board, I have been told to run VCC and GND lines all over the board. Spiderweb, "net", or star configurations are good. Also having them run along the edge of the board. I have heard that you can consider your 2-layer board smaller than what's actually edge cut, so that in the end just run VCC and GND lines around the edges. If this is a 4-layer board (though my first guess is not), then you don't have to do any of that.

I don't know where you intend on getting this printed. I personally use JLCPCB. They are super cheap and have many options. BUT having the board size any bigger than 10cm x 10cm increases the cost a LOT. If you are ok with a costly board, all good. Right now 5x 2-layer 10x10 boards are $2, and 5x 4-layer 10x10 boards are $8 and shipping isn't too bad. If you would be up for it, you could break this up into two smaller boards, but then you'd have to buy connectors and whatnot.

Did you do the routing yourself? It does look good! I very recently learned about auto-routers, in particular FreeRoute (or FreeRouting). It works pretty well with KiCad, and probably other programs, not sure what you are using. This REALLY opened up a whole new world for me, since I was able to really *squeeze* those chips in close together. What I am able to put on a little 10x10 board now was unthinkable to me just weeks ago.

Last thing, though I know it's very late in the game if you are looking at printing a board soon: When I was making my first board, I was wanting ALL of the options, gizmos, gadgets. LCD's, keyboards, buttons, SD cards, you name it I wanted it. And those 3x VIA's will get you there for sure! But, one thing I personally didn't realize was that as soon as I printed my board, it was obsolete. Meaning, I already had plans for the next one before the first board ever came in! I thought I would get it all done in one nice pretty board, and I'd be done and off to do software for the next 5 years. Nope. Instead, I was happy to get some blinky lights on the first computer, and then I got LCD and buttons to work. After that, I was ready to move on to bigger things.

This hobby is more expensive than I thought. Not that it's super expensive, but one board did not solve it all for me. I'm now *expecting* that, where my future designs are more plug-and-play, or at least cheap enough to toss and try something new. And that's ok early on because we are all learning. If you want to see growth, mistakes, and failures here are some topics to browse:

My first computer:
viewtopic.php?f=12&t=6818

My first printed board (a copy of the first computer without a mess o' wires):
viewtopic.php?f=12&t=6868

Attached is a picture of what my third computer will look like, I'm currently waiting on the boards to come in. You can see how the auto-router has let me really pack in the IC's and max out that tiny little board, while also leaving room for expansion.

I'm not a pro at this, by any means! I'm definitely still a newbie. But from one newbie to the next, that's my little bit of gathered wisdom.

Thanks!

Chad

You could save a one gate propagation delay by using 1/2 of a 74HC21 for your interrupts, then use the other half of it to buffer the clock as Jeff had suggested.

Do the two enables on the 40x4 LCD need to be controlled separately?

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Bill

sburrow - Thanks for that. This is auto-routed using EasyEDA, I've tried manually routing and that's just not for me at this point. For right now its just a 2 layer board and it will come in at about $13 for 5. I had looked at doing 4 layer (GND and VCC layers internal) but that jumps to $50. I could do that and I may on my next board, but for this tester board I decided not to.

Honestly this is my first go and it ended up being more than I expected as I wanted everything I wanted to play with on it all at once, hence the 3 VIA chips and both LCD ports :) Once I get this working and my playing / experimenting well underway I have another project in mind that will be a smaller board overall but a larger or at least more interesting project.

BillO - I missed the buffer on the clock and added that in, thank you. The E1 pin is the top 2 rows and the E2 pin are the bottom two rows on the display, they need split out so I can address each of the 4 rows. If they were tied together, I think the top and bottom two rows would both respond to the same commands. This is the datasheet I've been using for the 4004 display.