26) AM0..18 address counter
It breaks into two parts:
AM0..15 counter is located East from "25) transfer counter", not far from the MA0..7 pads.
AM16..18 counter is located East from the status Register $00, not far from the MA8 pad.
It generates the address for the REU DRAM, and selects one of the two DRAM banks.
;===
For the AM0..15 counter, the game is pretty similar to what we had in "24) A0..15 address counter".
We have two 8 Bit Registers: Register $04 for AM0..7, Register $05 for AM8..15.
Registers are cleared during RESET.
When the 6510 writes one of these registers, or when there is a RESET,
the contents of both registers are transferred into the AM0..15 counter.
When the 6510 reads one of these registers,
it actuall reads the contents of the AM0..15 counter.
;---
Special case:
If RELOAD is enabled (Bit 5 in command Register $01 is set),
the contents of the $04 and $05 Registers are reloaded
into the AM0..15 counter after completion of a DMA sequence.
To be more precise:
Register $01 Bit 5 goes into "31) tapeworm from hell",
which generates the UPDATE signal, telling the counter control circuitry
to reload the 16 Bit counter from the $04 and $05 Registers.
;---
A0..15 counter features the usual inverting\non_inverting ripple carry,
plus an 8 Bit carry lookahead mechanism that enables incrementing Bit 8..15 if there was an overflow in Bit 0..7,
enabling _another_ 8 Bit carry lookahead mechanism that increments Bit16..18 if there was an overflow in Bit 0..15.
Counter Bits change with PHI2.
"31) tapeworm from hell" enables counting with the cntAM_CEN# signal (low active).
If cntAM_CEN# is low, AM0..15 counter increments.
Attachment:
si8726_26_am0_am15_counter.png [ 264.25 KiB | Viewed 639 times ]
Attachment:
si8726_26_control_west.png [ 57.18 KiB | Viewed 639 times ]
Attachment:
si8726_26_control_east.png [ 45.02 KiB | Viewed 639 times ]
;===
For the AM16..18 counter (that's three Bits), the game is a little bit different.
We have one 3 Bit Register: Register $06 for AM16..18.
Register is cleared during RESET.
When the 6510 writes Register $06, or when there is a RESET,
the contents of Register $06 are transferred into the AM16..18 counter.
When the 6510 reads Register $06,
it actuall reads the contents of the AM16..18 counter.
;---
Special case:
If RELOAD is enabled (Bit 5 in command Register $01 is set),
the contents of the $06 Registers are reloaded into the AM16..18 counter
after completion of a DMA sequence.
To be more precise:
Register $01 Bit 5 goes into "31) tapeworm from hell",
which generates the UPDATE signal, telling the counter control circuitry
to reload the 3 Bit counter from the $06 Registers.
;---
AM16..18 counter features the usual inverting\non_inverting ripple carry,
counter Bits change with PHI2.
Attachment:
si8726_am16_am18_counter.png [ 166.5 KiB | Viewed 639 times ]
;===
Now for the DRAM bank select logic attached to the AM16..18 counter.
For AM16 and AM17, it reads the buffered counter outputs.
For Bit 18, it directly and unbuffered taps into the AM18 counter Bit.
BS (high active) goes through an inverting super buffer and becomes BS# (low active),
defining the size of the two DRAM banks attached to the 8726 inside the REU,
see "9) BS".
Note, that we are just talking about the configuration of the 8726 bank select logic here,
not about the _real_ size of a DRAM bank which physically is attached to the 8726.
;---
BS=low (BS#=high): two banks with 256kB of DRAM each.
if AM18=0, AM_bank1 goes high, selecting DRAM bank1.
if AM18=1, AM_bank0 goes high, selecting DRAM bank0.
Also, if the AM16..18 counter was 7 and rolls over to 0,
it is cleared by AMB_CLR (to me, this looks redundant).
;---
BS=high (BS#=low): two banks with 64kB of DRAM each.
if AM16=0, AM_bank0 goes high, selecting DRAM bank0.
if AM16=1, AM_bank1 goes high, selecting DRAM bank1.
Attachment:
8726_26_am_0_18_address_counter.png [ 404.26 KiB | Viewed 639 times ]
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