graeme.harker wrote:
floobydust wrote:
I'll make a few other observations...
1- What clock rate are you running the CPU at? I don't recall seeing it mentioned. Also, which CPU is it?
2- CA2... your ISR toggles it, but it's purpose is not described. Is it handshake to the external device?
3- Your ISR increments an index which is 8-bits. In short, after collecting 256 data inputs, you start overwriting your buffer space.
Finally, perhaps a schematic and picture of the setup you've built for this?
1) it's a WDC65C02S at 1MHz - nothing too crazy
2) CA2 is the OE# (output enable) of my downstream device
3) it's a standard circular "ring buffer" with read and write pointers (with a check to see if the buffer is nearly full) - pretty standard
Okay, so a quick look at your ISR, a couple things:
1- You're not managing your circular buffer head/tail pointer in the ISR, so you "could" get a buffer overflow.
2- A quick add on clock cycles, results in 55 clock cycles to execute. This limits your data transfer rate to about 18K per second (less all overhead in code elsewhere that runs to support this).
As there's more code running besides the ISR, you should examine how much over head it takes (in clock cycles) which will get you to how many transactions per second you can handle at 1MHz.
And the final question:
What is your maximum number of data transfers per second?
Login
Register
FAQ
Search
