BigEd wrote:
I haven't looked at the schematic, but BDD's comments remind me of something. If you have complex logic, where various inputs diverge and reconverge to produce a result, it's possible that the result will be glitchy - in fact it's relatively likely.
Going along with your theory (which I think is the likely scenario in this case) is the fact that propagation delays are somewhat random in nature, due to the usual device tolerances. Furthermore, temperature and/or voltage variations can vary the aggregate prop delay over the short term and further randomize things to where glitches can come and go with no obvious explanation.
MagerValp wrote:
If I'm reading the schematic correctly you're qualifying CS_RAM with PHI2, while R/W is connected straight to the SRAM's WE pin. You should instead be qualifying WE with PHI2, and CS_RAM should be decoded with as few gates as possible.
Those are points I earlier mentioned. The main concern with not qualifying /WE is the risk of corrupting data in an RAM cell that is incidentally selected as the address bus settles during Ø2 low. Hence the risk of corruption if /WE is asserted during Ø2 low.
A slightly more complicated situation exists with the 65C816, which drives the data bus during Ø2 low to emit the A16-A23 component of the effective address. Hence a device's /OE must not be asserted until Ø2 high to avoid data bus contention. Lacking that, a bus transceiver would have to be used for isolation.
Quote:
You have a lot of cascaded logic for the chip selects.
That he does. Aside from the potential glitching issue mentioned by Ed, there is the question of whether the logic in fact does what is expected. That can be hard to determine when gate after gate is used to generate an output.
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