For Altera EPM7064S (ATF1504 equivalent), I've found by trial and error that it can have 64 bytes of bootstrap ROM and still have enough logic fabric for other functions like decoding logic, bank select, and a simple serial port. I just completed a Z280 SBC design that uses EPM7032S (ATF1502 equivalent) to provide 32 bytes of bootstrap ROM, address decode, compact flash interface and a bit-bang I2C interface. I was quite surprised that a 32-macrocell CPLD can accommodate all these functions.
https://www.retrobrewcomputers.org/doku ... asmo:zzrcc
Bill

Would it be possible to ignore the address lines and instead implement a counter that serves the bytes in the order they're needed? Not sure if that would be any better or faster, but I've wondered if it's possible.

In a scheme where a processor is booted directly from a compact flash disk, a hardware state machine setup the CF disk to read then the data comes in as 256-word FIFO stream. My first Z280 SBC was boot off CF disk exactly like that. https://www.retrobrewcomputers.org/doku ... smo:z280rc
Bill