Yes, this is a case where the rising edge of Phi2 is probably a useful timing reference - I'm just making the slightly pedantic point that it isn't defined that way, although it's often described as if it is.

The relationship between address valid and the rising edge of Phi2 may not be explicitly defined, but it certainly has a guaranteed definition through the other 3 parameters. As well its value calculated as shown is valid for all NMOS and CMOS 6502 variants. For a 14MHz W65C02 it diminishes to 5ns minimum, but it is there and can be counted on.

Like if you have posts 5 meters apart and you specify 2 marks should be made on a line between the posts at 1 meter from one of the posts and at 3 meters from the the other post, you can be sure that there is 1 meter between the marks.

Using this reasoning, a precisely formulated relationship can be defined between all events in a 6502's cycle.

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Bill

Yup. Beginners and experts alike have successfully used Phi2, relying on the basic points which Bill outlined. Phi2 is the obvious choice, kakemoms, if you do in fact have access to it.

What you say is clearly true, but the simplest way to avoid being misunderstood by others is to stay focussed on cause and effect. For example, the fall of Phi2 is what causes the next address to become valid (after tADS has elapsed).

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Since everyone here were making a big point out of using phi2, I rewrote the whole code to use phi2 for all the timing. That did not help, in fact it made it much more unstable.

The 6502 can store data into the CPLD memory. It gets there and seems to be stable.

The 6502 reads data from CPLD memory, the CPLD responds with correct data pushed onto the bus. It gets on the bus just after phi2 goes high, and is kept there until at least 40ns after phi2 goes low again. Nothing gets into the 6502 unless I push the data much later. E.g. if the CPLD push the data onto the bus around 200ns before phi2 goes low (so its kept on the bus for at least 240ns), the 6502 mostly gets the data.

I think the problem is the TXB0108, so I am going to change that into another level shifter.

Well, I would choose perhaps 100 or so Ohms current limiting resistors between NMOS stuff and your CPLD. I would further prepare (say buy ) a 74HCT541 for level shifting the signals from CPLD to NMOS. But first I would try to use resistors only and avoid long lines (= additional capacitances).

Now that you can trim your timing relative to PHI2 I could not see a reason why this shouldn't work - except there is some other bus participant still active?

Thinking about this - can you run a loop where the 6502 is reading simply incremented data from your CPLD and place it in some (working) buffer. Perhaps one could get an idea of what is going wrong when seeing what is read. Perhaps there are patterns visible or a tendency for zeros or ones or or or ?

Perhaps you can perform this with regular (PHI2+40ns) and extended (PHI2+240ns) timing as well?

Okey, a poor choice of words from my side. In this particular situation, the use of PHI2 (and change of timing) did not seem to solve the problem at hand. So my guess is that its not related to timing; at least we can move that a couple of notches down the (debugging) priority list.



If I go two steps back; the original implementation (without PHI2) was running a program in the CPLD memory, so all the reading was working ok. It was the writing that seemed to have glitches (if the reading was glitchy, the program would have just crashed).

Now, it seems like the reading is glitchy. The program doesn't run at all unless its in a SRAM IC, and looking at the data in the CLPD from a real-time analyzer, its obvious that the CPLD pushes the correct data onto the 6502 bus, but for some reason the 6502 does not get it. The TXB0108 level shifter is between the CPLD and the 6502, so I will have to debug or change that somehow (I don't have the equipment needed here, but I will go to the local Makerspace tonight and see if I can set up things there). I will also test the extended PHI2 timing there (and maybe gather some interesting data in the process).

I finally managed to hook up a 4-channel scope to the computer bus and for writing (store D0=1) it looks like this:

Top is R/W line, second is PHI2, third line is D0 and fourth line is address access (which goes low when the CPLD memory area is accessed). All-in-all this looks fine (the instruction is a STA($ZP),Y which generates a memory read just before write)

Now, if I read the location (in the CPLD memory) with a LDA $addr it looks like this:


Which, as you see, the TXB0108 is a really poor driver! So you are right, I need something else than this TXB0108 to drive the really long lines into the old machine. I will test with some larger capacitors (there is currently a 0.1uF connected close to the TXB0108 power supply), but it is probably the general ability of the TXB to deliver enough current in a short time that is the problem. Since I have a SN74LVC4245ADBR at hand, I may test with this first.

What is driving the address bus, the 6502 or your circuit?
Is it even the 6502's address bus we are seeing?
Is your Phi2 taken at pin 39 or pin 37?

If that is the 6502's address but there is something not right in those scope plots.

I see the address changing coincidental with the rise of Phi2, I have never seen that before with any kind of 6502, NMOS or CMOS. Also your Phi2 looks too nice to be coming from an NMOS chip.

I have attached a scope trace I just took. It's an NMOS 6502A running at 1.8MHz. Yellow trace is Phi2 (at pin 37) and blue trace is A0. As you can see the address begins changing about 35ns after the falling edge off Phi2 - well within the specification of 150ns (max)

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Bill

I've successfully used the TXB0108 in an application where I connected a 5V CMOS microcomputer to a 3.3V FPGA. Two statements in the datasheet stand out to me in regards to the TXB0108: (1) it is intended for level shifting between CMOS systems, and (2) it has an internal circuit that is active for only 10ns which is used to produce the drive current.

One problem that I see in the application of the TXB0108 with an NMOS device on the B-side is that the device does not have a CMOS-compatible input. A second problem is that the capacitance of the B-side circuits is likely greater than what can be successfully charged by the device in 10ns. After that time, it looks like the device switches to a 4k series impedance; such a high impedance is not going to complete the signal transition very fast.

I don't think that hanging additional capacitance on the power pins of the TXB0108 is going to help the situation very much. A change to the SN74LVC4245ADBR is more likely to have the desired behavior.

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Michael A.

I assume line 4 on the trace is his /CE signal, post-decode. It's clearly gated by the clock.

The line of interest is line 3, which is the data bus. When driven by the 6502, it's fine. When driven by the level shifter, it really isn't.

Looking at the oscillographs I still think a simple series resistor will be sufficient. But a driver like MichealM is suggesting should be superior.

Yes, I see the less than ideal data when its driven from the shifter, although it should be good enough as an NMOS 6502 will see 2V as high on the DB. I just misunderstood what he meant by 'address access'.

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Bill

Address access is a line that goes low when the CPLD memory area is accessed by the NMOS 6502. E.g. when the CPLD needs to respond on the databus.

Thanks for all the help here, its really been helpful.