I tried the 1N60 diodes. Quite effective.

Set-up was a 74ACT04 inverter driving a 19cm wire loop to another inverter input a 1mHz. The diodes reduce the over shoot by 640mV and the undershoot by 400mV.

This is the select logic for 3 slots. If I went with 7 slots the 2 halves of the 139 would be replaced with two 138s giving up to 8 devices per slot. I don;t foresee needing this though so I'm currently just considering the 3 slot option.

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Bill

Alright, I'm back -- sorry for the delay!

From the look of this I guess you intend each I/O device to be activated by a gate (located on the I/O card -- added in color). The gate would require a Device Select in addition to the Slot Select for that slot. And the gate's output would activate the I/O device (also on the card, of course). I can see advantages to this arrangement, although to some extent it's a tradeoff due to the speed penalty of a third layer of logic. Presumably the tradeoff is something you judge to be worthwhile, according to priorities you've established for the project.

[Edit:] Can you tell us about how the 3 signals from the ROM Page Register get fed through the GAL before being applied to A16,15,14 of the ROM's? Does the GAL have a mapping function?

Here is an interesting speedup, useful when decoders are cascaded. The diagram below shows how an 'AC139 can be replaced by a 'CBT3253. (A fast one-of-eight decoder is also possible, using a 'CBT3251 instead.) Parts from the CBT family (and other low resistance FET switch products) have near-zero propagation delay for a signal passing through the switch itself. The same can't be said for the S1 and S0 select inputs, which incur some delay in establishing the desired connection, but that delay is hidden because it's concurrent with the delay of the GAL producing its output. IOW when the GAL output eventually goes low, the CBT output will go low at virtually the same instant. This basically eliminates one gate-delay from the overall path.

-- Jeff
ETA: the diodes can be omitted if you're willing to give the pullup resistors a fairly low value. Low values waste power but they can ensure the outputs go false quickly enough for the attached circuitry. The diodes are an alternative to this power waste, but lengthy output glitches can appear in applications which don't guarantee S1 and S0 are stable before the input goes low.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

No worries - been distracted myself.


Yes, that's the idea. In most cases there will only be a singe device on an I/O board, at least initially, then I could add them on as required. However, experiments have shown some trouble with my I/O bus scheme. The problem is not too much propagation delay, but rather the opposite. Using a 74ATC245 to drive the data bus is not allowing enough data hold time for some slower devices I want to use. Using a 74LS245 might help the slower devices, but may cause issues on the processor side of the bus ans I try to speed things up.


Using fast gates should make this work. Just have to solve my data hold time problem. Of course I could solve that by latching data for slower devices at the I/O board.


The GAL uses the higher processor address lines and the ROM page register lines to map to actual ROM addresses. The CUPL code is here:




They look like nice devices Jeff! I may incorporate them into this design - but I've spent a lot of time on the layout so far and would hate to have to begin again at this point. However, anything can and will happen. Nonetheless I'll have to pick some up to have a look see. Thanks for bringing them to my attention.

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Bill