A simple step towards reaching the goal is to replace the AVR with a microcontroller that's a bit faster, and/or has some nice peripherals to help with the job. A 80-120 MHz CPU with fast I/O capabilities and pin change interrupt should be able to service the 6502 in time.

That doesn't have to be a problem. A modern WDC 6502 will also happily run at 3V3, and so do the other parts.

Hi Andrew,

My apologies for going off-topic but I just wanted to mention that I've been brain-storming about a minimal ROM-less SBC design for several months now too but I think I need help from Daryl for the GAL. That is, I want to include a range of memory mapped I/O addresses for the PIC in the GAL, and a select input to allow boot-loading from the PIC into RAM. Since the PIC is providing the 65C02 clock, I thought it might be relatively simple for the PIC to slow down the 65C02 clock when processing one of its own memory mapped I/O requests. So the down-side would be slightly slower I/O to peripherals/resources on the PIC but the up-side would be connection to an array of new peripherals through the PIC (timers, rtc, adc, spi, i2c, storage, displays, etc.), all on a relatively small board (PIC, 65C02, RAM, and GAL).

Cheerful regards, Mike