So the delays are still additive, it's just that as you stray from that general point of room-temperature operation (including heat from the chips themselves) and MHz low enough to be counted on the fingers of one hand (in unary!), you'll start seeing the delays rise (possibly drastically) from the typical? Faster operation means more draw from the power supply and thus the power distribution, plus more frequent transitions raise heat generated by the chips... But overall, propagation delays are still additive?

Prop delays assigned to individual ICs are always additive...
Multiple levels of logic functions inside Programmable Logic devices are not additive. This is one very attractive feature of these devices.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Thanks for the backgrounder!


"Serial power distribution" is what is also called "daisy chaining"? I remember the Primer talking about a star-formation for power and ground lines.


Let me just take a moment to enjoy that question ... you just don't hear 24k being called too much anymore .

Seriously, though, this was just a scenario I thought up a while ago to fill up the whole address space. I'm still planning on 2 x 8k ROM, with one for the kernel/monitor, and the other for Forth, BASIC or whatever, and one ACIA and one VIA, with one 2-to-4 to address them all. I'll wait to get all fancy and clever till after I have one basic machine working ...

Thanks again!

One and the same. Star formation with 20 or 22 gauge wire is good.


All in all, RAM is more valuable. I'd only map in enough ROM to fulfill ROM needs. The more RAM you have the more ways you'll find to use it. Think of it like money.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!