I think this would require a minimum of 3 or 4transistors.


However, you could try a DTL circuit which should switch a bit faster:




Or even this:

_________________
Bill

Ill give it a try...

I suspect something like this ought to be sufficient. And, using a FET as BillO suggested, you could even eliminate the base (gate) resistor. But what IC is driving this circuit? CMOS would be preferable, because you need enough voltage to turn on the FET.

1K is probably more reasonable (drawing about 5 ma). And, looking at the bright side, the current drain is not continuous -- it only happens during the pulse that enables your latch -- or am I mistaken? Is the inverter output normally high or normally low? If the output is normally high then average overall current consumption will be quite low.

-- Jeff

and, like bogax said, put a 68pF or so capacitor across that input resistor to speed up the gate (inverter), getting rid of the delay from the RxC time constant there, the "C" being the base capacitance.

Does anyone have an oscilloscope, if yes could you try this circuits and see how they perform... I can test them myself, but without an scope, i can't really determinate how reliable they are...

It would be difficult for one of us to test as we do not know the full particulars about the drive and load characteristics in your circuit as well as your existing waveform.

_________________
Bill

The output is generated by glue logic, 4081, and the input goes to the OE* of the latch...
Suppose that the input is an ideal clock... The result of the test should be the the max clock at which toes circuits operate reliable...

4081? That one is not in my 4000-series data book; but 4000-series logic is extreeeeeemly slow! It is generally not suitable for glue logic for our home-made computers. If you're running that slowly though, maybe a home-made gate like that with resistors in the circuit could work ok. Computers have even been made with relays!

The address decoding is done by 2 x 74LS139, the r/w* and phase 2 logic is done by one CD4069UBE and one HEF4081BE. And there is another one 4081, but just for the latches OE* and LE signas... When i put the UM6502 i can get the thing going up to 4MHz, and it still works(don't know how reliable, but it kinda works...).

The 4081 is a quad dual input AND gate. Are you using all the gates in this package?

Another alternative would be to add another input diode to the DTL circuit to make a dual input nand gate. That way you could take the and gate from the 4081 out of the circuit altogether, even if you are using the other gates in the package.

Also traditional 4000 series logic is not really compatible with 74LS series. It might be causing some problems

_________________
Bill

the 74LS and 4000 logic come in contact in only one point, and this is where the latches are enabled.

Today my university professor let me use their equipment.
First thing i hook up my 6502 sbc to the oscilloscope, and the signals look good (@ 1mhz). After that i cranked up the frequency to 4 mhz, and every signal turned into a sinusoidal form... But the sbc still kinda worked...
After that i took a function generator and went to test the circuits above...
Things started to loooook creepy...
The case where only one transistor and 2 resistor is used looks horrible...
When a 1 to 0 transition(@500khz) occurs first the output goes in a dampening oscillation (@~10x input freq), and by the time half of the 0 time pases then it starts rising...
The 2 transistors/diode circuits looks much better under the scope, but still way to far from being a CD4069...
I tested also a old RCA 4001, and it works fine at 1 mhz, to a max of(2-3mhz). My new ST 4081 AND gate works kinda well at 2-3 mhz...
The 4069 perform better than any other circuit(it is only a not gate ).
At the end we ended up using a nice fpga board as a frequency source...
I think that 4000 series ic can be used for 1mhz circuits, but if the frequency is higher, things don't look very nice... So now i bought 74ls series for my mc68k sbc...
At the end i still don't know what i am going to do with that gate of mine...
What about tv vf transistors?

The oscillation is almost certainly from the construction method having wires too long and lots of stray inductance.

Depending on which transistor you ended up using, the slowness is probably from the RxC time constants. That's why the I²C interface method tops out at around 1MHz, and sometimes 400kHz. There are passive pull-ups on the two lines, clock and data, and everything else is open-drain circuits pulling them down. The key to speed is getting rid of the resistor(s). Notice how in the schematics BigEd posted at viewtopic.php?t=1634&postdays=0&postorder=asc&start=15 , all you see is MOSFETs--lots of them--but no resistors.

I noticed that wires that connected to my experimental board affected the measurements a bit...

Just a quick question: How low can i get the cpu clock, so that the NMOS 6502 works reliable. I got it down to a few Hz, and it still worked fine, but is it reliable?