tokafondo wrote:
It's a shame but I still haven't received the parts needed to manage the LCD module. I waited for more than a month for some LM2662 voltage inverters that never arrived, and then found that the shipment got cancelled at origin. So I had to order again from a different seller...
Meanwhile, I tried to attach a 1602A LCD module, to be controlled with the parallel port, but it seems I also need the inverters so that, also waiting.
So what I'm trying is to get is the '265s boot from the external EEPROM.
The usual way to do that is to burn the code you want to run in the EEPROM, and then put the "WDC" string in certain memory locations, so the ROM jumps to it and continue running from there.
But there is also another way, and it is bringing high the /BE line about 200ns
after the /RESET line:
Code:
When BE goes high after RESB goes high the BCR sets up the W65C265S for emulation. Port 0 and 1 are the address outputs, Port 2 is the data I/O bus and RUN is the multiplexed RUN function.
That means, as I understand, that you can make the '265s boot like a normal 65816 does, in 6502 emulation mode. I don't know if the owners of a '265SXB can mod that board to make this happen, by tinkering with the /BE line in pin 46 of X265_BUS connector.
I'm testing in a protoboard with ways to create that 200ns delay, having success there. I have to repeat that success in my board.
And then I have to copy the Mensch ROM Monitor in my EEPROM and get my board to boot with that delay.
I think that what is achieved this way is to get the '265s run only with
external memory. The internal 576 bytes of RAM and the 8K of ROM wouldn't be used at all. That would allow to work with a linear 32K RAM + 32K ROM of memory from the start, instead of messing around with the chip select lines to disable all the internal memory, a thing that's what usually done when booted from the Mensch Monitor.
I'm looking at the W65c134SXB board right now - it has a similar feature - ie. take BE low, then bring BE high some time after Reset goes high.
The board uses a simple RC network for the reset signal, so accurately timing it might be tricky, however my guess from reading the data sheet is that more likely to be a number of cycles from Reset going high rather than a fixed time and it looks like that might be 4 cycles (possibly 5) of the startup clock (which is off the 32768Hz xtal on the '134 SXB board)
So it may be possible to use a counter to gate BE high triggered by the Reset going high.
However, I have discounted this approach and will use the 'WDC' signature method - on the '134SXB it enables EEPROM from $8000 through $EFFF, checks for the 'WDC' signature, and if found JMPs to $8004. This check happens very early in the reset cycle, then my code at $8004 can disable the top 4K and swap-in the rest of the EEPROM and carry on.
Hopefully I'll have time today to adapt the code from Andrew Jacobs link
viewtopic.php?f=4&t=6339#p79164 and give it a go.
My 'gotcha' is that if I get it wrong, I don't (currently) have an adapter for the EEPROM chip for my programmers, so if I screw it up, then I'll have to wait until I can get an adapter, so plan A is not NOT set the 'WDC' signature bytes and just start my code manually by typing the command at the ROM prompt.
Cheers,
-Gordon
_________________
--
Gordon Henderson.
See my
Ruby 6502 and 65816 SBC projects here:
https://projects.drogon.net/ruby/
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