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PostPosted: Tue Sep 01, 2015 4:47 am 
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So I tore up a few fistfuls of wire!
Had to post a few photos, since I decided to have some fun while butchering my previous work.

Image
Ouch, that had to hurt!

Just for kicks, I left the power on, running the balls demo as I ripped as many wires from the Playfield Generator that I could grasp.
As I tore wires out in bundles, the demo just kept on running, not a single crash!

Image
Operating while the patient is fully conscious!

Bus collisions must have been rampant with the 245's all switching randomly after the wires were ripped from the board.
I guess the design is robust considering the amount of chaos it just took while running the demo!
You can see in the image that there seem to be hundreds of ball Sprites, but this happened because without the PlayField Generator working, the screen is no longer cleared by the background bitmap drawn to the Back Buffer. Because of this, the balls do not erase, they just pile up until the screen is filled or overwritten by the larger rotating boing balls.

Anyhow, I kept the power running as I pulled every last wire and chip from the PlayField section, and it never did crash!

Image
Dead bugs everywhere... oh the carnage!!

I pried up all the old chips with my Swiss Army Knife and left them piled in the barren wastelands that once housed the PlayField generator.
And yes, that is a grave-marker made out of wire sticking out of the board. RIP PlayField generator V1!

I will report back on how the new and improved PlayField Generator works at the target speed of 16MHz.

Later.
Radical Brad


Last edited by Oneironaut on Tue Sep 01, 2015 3:25 pm, edited 1 time in total.

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PostPosted: Tue Sep 01, 2015 2:29 pm 
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I love what you're doing. I have been watching your posts for last few weeks. I can't wait til you get close to completion and would love it if you made a PCB for hobbyists like myself to play with. I would love to interface it with a 65c816, a bagload of memory, and IDE and Ethernet :-)

If I could vote for one thing when you start working on the sound generator is to add digitally controlled analog filters (ideally low and high pass but low pass if only one is feasible) -- this is IMHO the killer feature in the SID that makes it sound so great.


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PostPosted: Tue Sep 01, 2015 2:57 pm 
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I second what Porcupine says, I love reading your updates. I'm completely new to the forum, and in fact signed up just so I could follow the thread and be notified when you post something. Reading your thread and others on the forum has inspired me to try and build something myself, even though I'm new to this. I'm still figuring out where to start - or rather, where I want to end up! - before placing an order for a bunch of ICs.


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PostPosted: Tue Sep 01, 2015 2:58 pm 
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porcupine wrote:
I love what you're doing. I have been watching your posts for last few weeks. I can't wait til you get close to completion and would love it if you made a PCB for hobbyists like myself to play with. I would love to interface it with a 65c816, a bagload of memory, and IDE and Ethernet :-)

If you want all those things, it's probably more convenient to use an FPGA, rather than 74xx series chips :-)


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PostPosted: Tue Sep 01, 2015 3:21 pm 
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Hey thanks! I am surprised at the amount of views this thread is actually getting... I guess there is still an interest in old-school hacking after all!

As for the Sound Generator, it is definitely getting digitally controlled analog filters!! That was a must right from the start.

Here is what I have in mind for the Sound Generator so far...

1024K of dedicated sound sample memory.
4 independent voices, each taking turns reading from the memory.
Stereo output, with 2 voices mixed per channel.
Each voice will have the following features...

- Volume control (8 bits)
- Frequency control (16 bits)
- Sample start address (20 bits)
- Hi / Lo pass filter (8 bits)

I may add channel filters as well as follows...

- Channel 1 : digital reverb delay
- Channel 2 : analog distortion

I have not really described how the sound system is going to work, so here is my plan...

Each voice has its own 16 bit counters, reset by dual 688s loaded from dual 574s (frequency control).
The main sound clock is sliced into 4 by a 4017 counter, giving each channel sequential time.
During each slice, a channel sends its address to the SRAM, and then pumps a byte to a 574.
The 574 feeds an R2R DAC, and then a 741 op amp, where another DAC (volume) mixes the output.
A sample will stop when it reads a 255 value. A 688 triggers a 7474 to halt that channels counter.

Effects are also similar, with 574s feeding R2R DACs and the appropriate analog circuitry.
The Hi / Lo pass filter will be based on a guitar Wah pedal I made in 1984!
For the reverb, I am looking at doing that all in logic as well using counters and SRAM.

I may also add an LFSR filter that can "randomize" the bits for a cool scrambling effect.

Anyhow, thanks for the kudos! This project has been an absolute blast to build!
Equal efforts will be put into the cabinet design and website to detail this build when it's ready.

Oh, and yes I do plan to make PCB. If there is actually enough interest, I would do parts, boards or kits.
Not doing this for $$$, so it would be more of a community purchase for boards to keep costs down.

Cheers!
Radical Brad... Breadboard Baron and Czar of wire.


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PostPosted: Tue Sep 01, 2015 4:49 pm 
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Wow, that's a MEGA breadboard.
I just discovered this thread via a link from Blondiehacks.

I've been looking for a good source for hookup wire the right gauge for these breadboards, thanks for the idea of using CAT5 wire (well actually I'm using CAT3 wire, same thing just that the pairs aren't twisted as tightly).....

A comment on those '154's. If you made an exception about using SMT memories on socket adapters, why not the same for SMT 154's and similar parts no longer made in DIP packages?

Oh and on over clocking atxmega's ... I've seen atmega644's overclocked in a retro gaming project to over 25mhz, and atmega1284's overvolted to 6 volts and overclocked as well. Nice to know that the Xmega can handle it, especially the '384 version.


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PostPosted: Tue Sep 01, 2015 5:58 pm 
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Oneironaut wrote:
Hey thanks! I am surprised at the amount of views this thread is actually getting... I guess there is still an interest in old-school hacking after all!

Not only a very popular thread, but you've brought a new high score to the number of concurrent visitors to the forums!
Quote:
Most users ever online was 254 on Wed Aug 26, 2015 3:05 am

Previously
Quote:
Most users ever online was 183 on Wed Jun 27, 2007 3:13 pm

Previously
Quote:
Most users ever online was 44 on Sat Jul 09, 2005 3:02 am

You really must connect that 6502 to the breadboard to make it all authentic!


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PostPosted: Tue Sep 01, 2015 9:34 pm 
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I posted a link to this thread to HackerNews last week:

https://news.ycombinator.com/item?id=10120500

That probably accounts for the burst in traffic to some degree.


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PostPosted: Wed Sep 02, 2015 7:58 am 
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Nicely done! Interesting that HN brought more visitors than Hackaday, which featured the project on the 11th. I'm always impressed at the level of informative and polite discussion on HN.


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PostPosted: Sun Sep 06, 2015 2:40 pm 
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Working on the Playfield redesign now, and it is showing promise.
Will post an update when I have the new version is fully smoke tested.

Radical Brad


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PostPosted: Thu Sep 10, 2015 3:08 pm 
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Still kickin', just been busy!

I have had only a few hours to smoke test the new PlayField Generator design, and so far it looks as though an increase in speed will be possible. There are some glitches as the comparators reset the 590 counters, but this is to be expected as the pathway through the 688 and 7474 will add at 30ns to the state machine. I will be dealing with this by allowing the x-counter to pull a reset at 400 rather than 399 (video draws from 000-399). This adds an extra cycle (off the screen) to allow the y-counter to wrap slower than the x-counter. Having this happen at location 400 means that no glitchy pixels are drawn to the Video Memory.

"Glixels"

This is what I call glitchy pixels!
There shall be no Glixels in this design!

Will post as soon as I have some time to hide out in my quiet basement lab and work on the project.
Implantation of the 6502 is so close that it's difficult to not jump ahead, but things MUST be perfect before the AVR retires for good.

Cheers,
Radical Brad


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PostPosted: Thu Sep 10, 2015 10:15 pm 
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Oneironaut wrote:
...Will post as soon as I have some time to hide out in my quiet basement lab and work on the project.
Implantation of the 6502 is so close that it's difficult to not jump ahead, but things MUST be perfect before the AVR retires for good.

Cheers,
Radical Brad

Retire that AVR! :lol:

Do you have any future desires to learn HDL and "make your own IC's" in FPGA's? Do you fear working at different voltage levels?

Going back to lurking...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502


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PostPosted: Fri Sep 11, 2015 12:19 am 
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Yes, the poor over-volted XMega will soon get a rest!

FPGA... if you look back on this thread, you can see my many FPGA / CPLD video designs.
Have done everything from NTSC to HDMI in Verilog.
Not as fun as retro logic!!!

Brad

ElEctric_EyE wrote:
Oneironaut wrote:
...Will post as soon as I have some time to hide out in my quiet basement lab and work on the project.
Implantation of the 6502 is so close that it's difficult to not jump ahead, but things MUST be perfect before the AVR retires for good.

Cheers,
Radical Brad

Retire that AVR! :lol:

Do you have any future desires to learn HDL and "make your own IC's" in FPGA's? Do you fear working at different voltage levels?

Going back to lurking...


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PostPosted: Fri Sep 11, 2015 12:29 am 
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Oneironaut wrote:
...FPGA... if you look back on this thread, you can see my many FPGA / CPLD video designs.
Have done everything from NTSC to HDMI in Verilog.
Not as fun as retro logic!!!...
Cheers,
Radical Brad

Ok, to each his own! Cheers... Personally I would find a 30ns delay on a HCTTL device such a bore.

EDIT: I meant boar (pig on timing), not bore as in bored.

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PostPosted: Fri Sep 11, 2015 2:38 am 
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Pushing basic 7400 logic to do things that seem almost magical... that's what makes it fun.
Loading cores on an FPGA is akin to shooting a squirrel with a bazooka... not much sport in it!
Ok, it's not that bad, but you see where I am going with it.
My goal is not the destination as much as the journey.

Brad

ElEctric_EyE wrote:
Oneironaut wrote:
...FPGA... if you look back on this thread, you can see my many FPGA / CPLD video designs.
Have done everything from NTSC to HDMI in Verilog.
Not as fun as retro logic!!!...
Cheers,
Radical Brad

Ok, to each his own! Cheers... Personally I would find a 30ns delay on a HCTTL device such a bore.

EDIT: I meant boar (pig on timing), not bore as in bored.


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