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BigDumbDinosaur
PostPosted: Tue Feb 12, 2013 9:16 pm 
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Dr Jefyll wrote:
BigDumbDinosaur wrote:
As the '816 is a fully static device, it's reasonable to assume that all timing values, as a percentage of machine cycle time, stay constant over the range of Ø2 values. So by using the specs for 14 MHz and some simple extrapolation, one can predict with good confidence how the circuit will behave at 20 MHZ. I hope to soon find out if I'm on the right track.
The right track, eh? I know you're an avid railroad fan -- and it looks as if your interest in trains is influencing your vocabulary!

Actually, "on the right track" has been part of spoken English since the 19th century. Many of my relatives on my mother's side of the family were railroaders (all are/were Canadian, going back to the 1860s when their ancestors immigrated from Ireland) and just about all worked for the CN, so the expression was common. Ditto for being "off track" when someone was diverted from their intended task. My grandfather, who was a CN engineer back when water was boiled to make trains go, often used railroad slang to describe everyday activities. My favorite was "oiling around," the term normally used to describe the task of lubricating the rods, valve gear and such of a steam locomotive. When grandpa used that term at home, it meant he was enjoying a sip or two (or three) of whisky. :lol:

Quote:
But let's see if I follow what you're saying. Maybe you're not on the right track. Timing values do not stay constant as a percentage of machine cycle time.

An example would be helpful. tADS (the delay from phi2 low until A15-A0 are valid) is listed as max 30 ns. At 14Mhz this is about 43% of the 70 ns cycle time. If we choose a 140 ns cycle time (7 MHz), tADS is still max 30 ns -- now about 21% of the cycle time. If we shorten the cycle time, same thing -- still max 30 ns, but the percentage has changed again.

So, my diagram is only to scale for the case of 14 Mhz (a 70 ns cycle). If the cycle time is altered you'd need a new diagram if you want to remain in scale -- which is probably why scaled timing diagrams are uncommon; you need a new diagram for every operating frequency.

You make some good points. However, I am suspect of the published '816 timing specs for several reasons, not the least of which is my observations on POC V1 at various Ø2 frequencies indicate that the timings seem to be proportional, not fixed, as the specs seem to imply. Also, Garth Wilson has often pointed out that the data sheets for the various WDC devices tend to paint a conservative (sometimes gloomy) picture of their capabilities.

Something else worth noting is that WDC generally doesn't publish the temperature range over which the data sheet specs apply. They do specify a reference temperature of 65° C for the Idd vs. Vdd and Fmax vs Vdd graphs. However, it is highly unlikely that operation at that temperature will occur in the usual course of events. I think they publish a worst-case set of specs, when in reality most of our designs operate at or near room temperature, and thus are able to perform much better than what one might thing.

In any case, I've tested with Ø2 at 1, 4, 8, 12.5 and 15 MHz, and have noted that the bus timings as a percentage of machine cycle time don't change much, especially the all-important tBH bank address hold time. My test setup was on a dual HP 275 MHz scope triggered by the low-going Ø2 clock, with a NOP generator used in place of a ROM (NOTE: the NOP generator that Lee Davison describes on his website won't work properly on an '816 system, as it causes bus contention during Ø2 low when the bank address is present). I tied all data lines together through Schottky diodes so I'd have a wired-OR scenario to cleanly differentiate between when D0-D7 was being driven with the bank address and when the MPU was seeing the NOP opcode.

I haven't run POC V1 at 20 MHz, but I suspect that I will see proportionate timing at that speed (we know the '816 can run at 20 MHz without trouble). If I do then it means that the timing margins are relatively independent of clock rate and thus highly predictive, as well as being conservative.

Quote:
ps- thanks for the remarks on ABT series devices -- are they preferable to BCT? Among the 5V-capable families, what's best? There are so many families now it's getting like alphabet soup! This could merit a new thread -- it's not just an '816 issue.

Although I haven't done an exhaustive comparison, ABT is generally faster than BCT, in some cases by a nearly 2 to 1 factor. For example, typical tPLH (input to output low-to-high prop time) of a 74BCT373 octal D-latch at 25° C is 5.9ns. The same parameter for a 74ABT373 is 3.9ns, a 66 percent improvement. The 74ABT573 (functionally equivalent to the 'ABT373) is even faster at 3.2ns. Aside from speed, ABT's claim to fame is its high drive strength, with a typical source rating of 32ma and a sink rating of 64ma. Naturally, such drive strength is of value in heavily loaded bus situations, such as described by Daryl in his SBC 3 design. Similar to the ABT series is the FCT series. Most of the ABT and FCT series are produced in SMT packages, many being SOIC (50 mil). You won't find much in PDIP, but I don't see that as a limitation anymore. The SOIC packages are easily hand-soldered. If I can do it, all you younger guys certainly can! :P

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BigDumbDinosaur
PostPosted: Tue Feb 12, 2013 9:23 pm 
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BigEd wrote:
On a separate note, I wonder if the '802 drives the bus during phi1 - I'd bet that it is the same die, with a different bond-out.)

The '802 was guaranteed to be bus- and pin-compatible with the 65C02. Hence the bank address could not have been allowed to be applied to the data bus during Ø2 low, as doing so would have broken compatibility. Also, although my memory of the '802 has greatly faded (I last looked at its data sheet in the mid-1990s), I do recall that it produced the PHI2O and PHI1O signals that are present in the 'C02. Therefore, the die had to have been different in some respects.

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BigEd
PostPosted: Tue Feb 12, 2013 9:29 pm 
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I can see that guaranteed compatibility might well prove the point that the data bus must be undriven during phi1, but I wouldn't follow the other conclusion: it's easy enough to put extra pads on a chip and bond-out different subsets of them to the pins to make different products. And it's terribly difficult to design a chip, so even two related designs (like 6501 and 6502) is a more costly project than to make a single die with two bond options.

Having said, this die shot has 40 bond wires and no obvious sign of spare pads, which counts against my hypothesis!
viewtopic.php?p=15729#p15729

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Ed
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Dr Jefyll
PostPosted: Wed Feb 13, 2013 3:31 am 
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BigDumbDinosaur wrote:
I am suspect of the published '816 timing specs for several reasons, not the least of which is my observations on POC V1 at various Ø2 frequencies indicate that the timings seem to be proportional, not fixed, as the specs seem to imply. Also, Garth Wilson has often pointed out that the data sheets for the various WDC devices tend to paint a conservative (sometimes gloomy) picture of their capabilities.
It's quite plausible to say the published figures are conservative, but to say that in reality the actual delays scale proportionally with clock speed is a provocative statement -- I got derailed on that one!
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In any case, I've tested with Ø2 at 1, 4, 8, 12.5 and 15 MHz, and have noted that the bus timings as a percentage of machine cycle time don't change much, especially the all-important tBH bank address hold time.
What else did you test besides tBH? Is this diagram a reasonable representation of what you used? (I like simple tests.)


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65816 test1.gif
65816 test1.gif [ 4.9 KiB | Viewed 15546 times ]

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BigDumbDinosaur
PostPosted: Wed Feb 13, 2013 5:43 am 
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Dr Jefyll wrote:
BigDumbDinosaur wrote:
I am suspect of the published '816 timing specs for several reasons, not the least of which is my observations on POC V1 at various Ø2 frequencies indicate that the timings seem to be proportional, not fixed, as the specs seem to imply. Also, Garth Wilson has often pointed out that the data sheets for the various WDC devices tend to paint a conservative (sometimes gloomy) picture of their capabilities.
It's quite plausible to say the published figures are conservative, but to say that in reality the actual delays scale proportionally with clock speed is a provocative statement -- I got derailed on that one!

So it would seem. I imagine the internal prop time through the gates is vanishingly small but cummulative (MPU design is not my area of expertise).

Quote:
Quote:
In any case, I've tested with Ø2 at 1, 4, 8, 12.5 and 15 MHz, and have noted that the bus timings as a percentage of machine cycle time don't change much, especially the all-important tBH bank address hold time.
What else did you test besides tBH?

Just tBH. That is the most stringent timing value that must be considered in a real-world design.

Quote:
Is this diagram a reasonable representation of what you used? (I like simple tests.)

Not quite. The NOP part drives D0-D7 through a 74ABT541 buffer, which is gated to the high-Z state when Ø2 is low, thus preventing bus contention. The balance of the circuit is the same. I used the buffer to simulate what would happen in a real application. It's prop time input to output is 2.6 to 2.9ns. I'll dig up the schematic some time and post it.

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Dr Jefyll
PostPosted: Wed Feb 13, 2013 9:19 am 
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Quote:
I've tested with Ø2 at 1, 4, 8, 12.5 and 15 MHz, and have noted that the bus timings as a percentage of machine cycle time don't change much, especially the all-important tBH bank address hold time.
Quote:
What else did you test besides tBH?
Quote:
Just tBH. That is the most stringent timing value that must be considered in a real-world design.

When you report about "the bus timings" -- and even center one out for special attention ("especially the all-important tBH") -- readers are left with the impression that tBH was just one of a list of values included in your analysis. Aren't you maybe kinda stretching things? What's up with that? You have a nice prose style when you write, but knowing when to stop is a valuable skill, too. I'm trying to say that in a nice way, even though this is via email (sort of).

Be that as it may, hats off to you for actually performing some sort of experiment. It's something I wanted to do myself and haven't gotten around to. :|

cheers,
Jeff

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BigDumbDinosaur
PostPosted: Thu Feb 14, 2013 5:09 am 
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Dr Jefyll wrote:
When you report about "the bus timings" -- and even center one out for special attention ("especially the all-important tBH") -- readers are left with the impression that tBH was just one of a list of values included in your analysis. Aren't you maybe kinda stretching things? What's up with that? You have a nice prose style when you write, but knowing when to stop is a valuable skill, too. I'm trying to say that in a nice way, even though this is via email (sort of).

Be that as it may, hats off to you for actually performing some sort of experiment. It's something I wanted to do myself and haven't gotten around to. :|

cheers,
Jeff

Sorry if I gave the impression that I was observing a laundry-list of items. tBH was the only one to which I was paying close attention. However, I also watched RWB, VDA and VPA to see what they were up to with different speeds. I didn't see anything that I didn't expect to see.

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Dr Jefyll
PostPosted: Thu Feb 14, 2013 5:58 pm 
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Well, it's an interesting subject. If you do collect some detailed information I hope you'll share it with us.
BigDumbDinosaur wrote:
Most of the ABT and FCT series are produced in SMT packages, many being SOIC (50 mil). You won't find much in PDIP, but I don't see that as a limitation anymore. The SOIC packages are easily hand-soldered. If I can do it, all you younger guys certainly can! :P
Easily hand-soldered? Heck, you're doing better than I am if "easy" is the word that comes to mind! But the .050" stuff is do-able.

Although it's slightly off-topic, I will quickly mention that proto-board using .050" grid is available. Unfortunately the selection is very limited; I know of only two examples, the Vector 8021 and the 8028. The 8028 is actually a combo board with areas of .100", .050" and 2mm grid.

cheers,
Jeff


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GARTHWILSON
PostPosted: Thu Feb 14, 2013 6:56 pm 
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Dr Jefyll wrote:
Although it's slightly off-topic, I will quickly mention that proto-board using .050" grid is available. Unfortunately the selection is very limited; I know of only two examples, the Vector 8021 and the 8028. The 8028 is actually a combo board with areas of .100", .050" and 2mm grid.

Twin Industries has them too, and they tend to be much, much cheaper than Vector. I saw them at the local Fry's Electronics. See https://twinind.com/index.php/products/ ... ng-boards/ . The holes on .050" centers are too small to put regular WW sockets into though. Another alternative if you really don't want to make a custom board is to use the SOIC-to-DIP adapters. They tend to be expensive; but buying several would still be a lot cheaper than getting a PC board made.

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clockpulse
PostPosted: Thu Feb 14, 2013 9:28 pm 
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I have used the WDC schematic for bank latching using an ACT573 and the ACT245 and had stable operation with a 10mhz clock. The rest of the glue logic was HCT based and the circuit was wire wrapped. Just keep the wires as short as possible and use plenty of bypass caps. (soldered in if possible) as close to the chips as you can get.
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BigEd
PostPosted: Thu Feb 14, 2013 10:26 pm 
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Hi Clockpulse - good to hear about your success. Could you comment please on how short your wires are and close the caps are to the chips? I prefer to see "a few inches" and "less than half an inch" to "as close as possible", because it's much more helpful to anyone without the experience.

Thanks!
Ed
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clockpulse
PostPosted: Thu Feb 14, 2013 11:19 pm 
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BigEd wrote:
Hi Clockpulse - good to hear about your success. Could you comment please on how short your wires are and close the caps are to the chips? I prefer to see "a few inches" and "less than half an inch" to "as close as possible", because it's much more helpful to anyone without the experience.


It's not easy to keep the leads on the caps. short when using wire wrap sockets but I try to keep them right next to the socket or between sockets with a distance less than half an inch. Supply and Ground rails help. In some cases I have soldered the caps on the bottom straight between the Vcc and gnd pins of the chip (best for buffer drivers like the 245).

I 'try' to keep the wire wrap wires in the 2 to 3 inch range. Of course when you're running the data and address busses the total length might add up to 6 or 7 inches. A board with a ground plane helps, and keep the wires against the board.
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BigEd
PostPosted: Fri Feb 15, 2013 8:05 am 
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Thanks!
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Arlet
PostPosted: Sun Mar 03, 2013 2:34 pm 
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BigEd wrote:
On a separate note, I wonder if the '802 drives the bus during phi1 - I'd bet that it is the same die, with a different bond-out.)

According to WDC's Programming the 65816 it's a very similar die, but with differences in the metal layer(s):
Quote:
The 65816 and the 65802 were designed to bring the 65x family into line with the current generation of advanced processors. First produced in prototypes in the second half of 1984, they were released simultaneously early in 1985. The 65816 is a full-featured realization of the 65x concept as a sixteen-bit machine. The 65802 is its little brother, with the 65816’s sixteen-bit processing packaged with the 6502’s pinout for compatibility with existing hardware.

The two processors are quite similar. They are, in fact, two different versions of the same basic design. In the early stages of the chip fabrication process they are identical and only assume their distinct “personalities” during the final (metalization) phase of manufacture.
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BigEd
PostPosted: Sun Mar 03, 2013 3:27 pm 
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I stand corrected - thanks!
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