Tancor wrote:
I must have mis-understood, I was under the impression that greener was going to use the pic for handling the graphics and such and ultimately create the game base of the system using a 6502 type cpu - at the time when I had written it, the only future design I had noticed on greeners site was
I was going off what he wrote
here. I know he is planning on a 6502-based system in the future, but his immediate needs are for the PIC system.
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as I recall, you can actually write to video ram during a refreshcycle - this is what causes the shearing of the display that happens if you don't wait for the verticle sync (at least in mode x)
*EDIT*: let me make a slight modification to this paragraph - rather then just saying "during the draw cycle" I should say rather at periods in-between when pixels are being drawn - at least this is how I understood the issue, I may be very mistaken in how it works, but I just wanted to clarify my understanding, if I'm wrong, if you could explain it in more detail I'd be most appreciative - my favorite thing is to learn and understand things, not give wrong information
The shearing occured when you placed something on the video card's internal data bus at precisely the same time the video dot shifter was reading data from the bus. As a result, either incorrect data or NO data was displayed during that fetch cycle, due to bus contention.
However, except for the original IBM VGA and some early Trident VGA cards, I haven't seen this ever be a problem in years and years. Most video cards are intelligent enough now to insert wait states as appropriate, after filling a (usually) 16-byte deep write-queue FIFO (as I understand current hardware implementations; the FIFO being flushed every horizontal sync period).
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But I can see your point in multiple back buffers beyond 2, but, I had already mentioned that using video ram for sprite storage was a common decent practice - I didn't really see a use for generating so many extra back buffers with directx, but I can see how having one backbuffer with just background another with foreground, etc. would work out fairly well.
I guess I just don't see the difference between what you're describing and what I'm describing. If you have one frame buffer, and one "back buffer" per displayed object, then to render the screen, you need to write into the frame buffer from lowest to highest priority object (where high priority objects appear "on top of" lower priority objects) memory. Only the rectangle which is "dirty" needs updating; this minimizes CPU and/or blitter overhead. But the point is, each object has its own frame buffer which can be drawn into. The screen might be 1024x768, but the mouse pointer itself might be only 16x16.
Modern GUIs extend this to ALL visual elements, by describing their screens in terms of scene graphs and even "software" display lists (the former is used by Apple's MacOS X, for example; display PDF).
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diagrams, especially for composite NTSC output) I'd say if it did vga that'd be great, I'd love to have access to NTSC though.
NTSC and PAL are technologically more difficult for me. It would actually be much easier for me to use "luminance" and "chroma I&Q" instead of R, G, and B channels for NTSC video (I'm sure it's the same for PAL, but I have absolutely zero experience dealing with PAL at all). Otherwise, I'd need to find some way to convert R, G, and B into YIQ form. I'm sure there are dedicated chips to do this; if so, that'd make things somewhat easier for me.
NTSC monochrome would be even easier for me to support, though.
BTW, many people are using 6502s and 65816s clocked at 1MHz or 2MHz still. This bus speed really isn't suitable for 640x480x256 color displays (it'd take anywhere between 2.5 to 1.25 seconds just to update the whole display; plus, drawing individual characters on the display will be quite visible and noticable). Therefore,
* Are you looking for unified memory architecture (e.g., system RAM and video RAM are the same), or split RAM architecture? If you do want a UMA, what kind of system RAM bandwidth are you willing to afford?
* What video resolutions are you interested in? What kind of color depth are you looking for?
* If the hardware can provide any services to make writing the software easier, what would those services be, ideally?
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Quantity - well, that's a tough one, can't say how many I'd want or use. at least 2, possibly 3, possibly more if I ever come up with something cool. Since I do this (tinkering with 6502, modifying kits, etc.) as more of a hobby I wouldn't have a huge quantity need. But, it would be nice to have if ever made available.
I'll wait until I hear back from more people, if any at all, before making a final decision. It's just that I don't want to invest $300 into a development kit, only to "just barely" break even, if that. In fact, even if only 6 chips were purchased and I priced them at $30 each, I'd still be taking a huge loss on the project.
Perhaps I can augment my lineup with a good and solid general purpose chipset too, including a much needed update to the 6551 ACIA (gosh, that's the limiting piece of hardware I'd ever seen for the 65xx-family support peripherals!). Heck, maybe I can even finally give the 6502 community the ability to use USB 1.1 devices too. And then there's the all-important DMA and sound capabilities that I'm sure quite a few would like to have as well. SID chips are getting hard to find now-a-days, and the Yamaha(-clone) chips are limiting in their own little ways too.
Any suggestions for what you'd like to see most? If I can amortize my investment across a whole family of peripherals, I think that'd be best.
You know, it's funny -- Garth Wilson has been trying to get me into doing this for
months. Maybe now is the right time.
Mike, if possible, I'd like your input on this as well. What do you think? What kind of market would be for something along these lines? Would you be willing to promote these products to other 6502 entheusiasts in the hopes of getting higher sales? If so, what kind of volumes are we looking at?