I am just putting together a 6502 circuit comprising the processor, a 2732 Eprom, a 6116 Ram and two 6522 VIAs for a traffic control project. From the knowledge gained from Chris's project, I clocked the 6502 from a 1Mhz-crystal controlled clock circuit. I conconnected the 6502 as instructed especially the NMI, IRQ, RDY, RESET & SO pins high using a 3K pull-up resistors. A two channel scope was connected; one to the clock input pin 37 and the other to one of the address outputs. On switching the power and connecting the reset pin to ground momentarily, both clock and the address signals appeared on the scope. However the address signal disappeared after some time but the clock remained. On resetting again, the address signal reappeared and disappeared again. I then disconnected the wires to the other chips and with the 6502 alone the same condition persisted.

I need assistance with decoding using 74LS138 chip. In the Chris's project example signal /Y7 was connected to enable the EPROM at the memory mapping of E000 - FFFF. The I/O mapped to 8000 - 9FFF was enabled with the signal /Y4. I need to be enlightened. Now my other questions are: Will signal /Y0 enable the 32K RAM at memory map of 0000 - 7FFF? If the I/O is mapped to A000 - AFFF which 74LS138 signal will enable it? Why must the ROM be at the top bank of the memory map? Will it not work at a lower level of the memory map? Please help as your answers will speed up my pet project.

Thank you.
folorunsoa

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folorunsoa

Which address pin did you connect to the scope?

You need the ROM at the top of the address map as the reset vector is located at FFFC & FFFD.

Also, what address pins are connected to the '138 inputs?

If it is connected like this,
A15 -> C, A14 -> B, A13 -> A, and G2A, G2B -> gnd, G1 -> VCC

then
Y7 decodes $E000-$FFFF
Y6 decodes $C000-$DFFF
Y5 decodes $A000-$BFFF
Y4 decodes $8000-$9FFF
Y3 decodes $6000-$7FFF
Y2 decodes $4000-$5FFF
Y1 decodes $2000-$3FFF
Y0 decodes $0000-$1FFF

To get all 32k for RAM, tie A15 to the RAM /CS pin and do NOT use the '138's Y0 thru Y3 outputs as these will decode addresses in the RAM space. Since your RAM is a 6116 (2kx8), you could connect the RAM /CS to Y0 and leave the other space open for other IO/memory.

You should have RAM mapped to $0000 thru 01FF to allow zero page and stack operations.

Hope this helps!

Daryl

This sounds somewhat similar to the problems I was having with my 65816 in the Kestrel design. What kind of 6502 is it? Are you *positive* that the clock skew requirements of the processor are being met by the clock circuitry? 80% of the problems I had with the Kestrel were solved by swapping out the clock generator circuit for one with 5ns or faster skew (in particular, a clock oscillator can). The other 20% were software bugs.

one reason the address disappears is that the processor is executing code from the ROM and then moving to an address range that does not cause the address pin you are monitoring to change.

For instance, if you monitor A14, and the code jumps to an address in ROM from $8000-$BFFF, A14 will stay low.

You can try Lee Davison's NOP generator to test your address lines.
http://www.6502.org/mini-projects/nop-gen/nop-gen.htm

Daryl

I have to ask, um, what's in your EPROM?

If it's a brand-new one(doubtful) or if it has been erased,
it'll be filled with $FF.
For the 65C02, $FF is a valid opcode. This situation
would, on RESET, begin executing code at addr. $FFFF.
The instruction would then be: BBS7 $nn $nn, where
nn is whatever bytes were found at addresses $0000
and $0001 respectively. After that, the CPU could be
executing code from RAM which doesn't contain any
valid 6502 program code. However: I'm not sure, but
I don't think there any invalid opcodes that cause the
65C02 to "lock-up" or stop outputting addresses.

Not so the plain NMOS 6502; there are several invalids
that may cause lock-up, but I don't know if it would
halt address bus activity. Anyone?

Assuming a used EPROM, the situation is similar if it
doesn't contain properly aligned 6502 program code.

So, I have to ask : Have you programmed your EPROM
prior to testing? If so, perhaps you could post your program
code here so these folks could look it over and see if anything
leaps out.

I'm not meaning to insult here, but one thing I've learned
as a troubleshooter is that one must often ask the most
obvious questions first, however silly those questions seem.

Good luck with the pet project!

Brian

<more>
You mentioned this:

That is to be expected, especially when using the NMOS parts (see my last post).
Operation of the 6502 with nothing tied to its data bus will result in utterly unpredictable behavior. At a barest minimum, use the aforementioned
NOP generator.

Also: decoupling. It is *crucial* that EACH IC COMPONENT have a decoupling capacitor connected between Vcc and Vss pins (0.1uF ceramic works well). This is especially important if you're using solderless breadboard.

Regards,
Brian

I have been out of my home base for a four-week workshop; hence the delay in my reaction. All the same big thanks to you ALL that have responded to proffer solution for my problem.

To start with, I want to state that I am using an NMOS 6502P, never been used but twelve years old stocked under a tropical environment. So also the ram, eprom & the VIAs 6522. They run on 1Mhz frequency.

I read somewhere that the Sync signal on Pin 7 of the 6502 is regular & continuos; so I shifted my monitoring points to Pin 39 Clock O/P and Pin 7 for the sync. output signals. From observation, the sync frequency is half of the clock which is 1Mhz. The decoupling capacitors (0.1uF) are in place and this affected positively the running of the processor. However, it starts running and after sometime it stops and starts running again.

When the 6502 is running, the clock output at Pin 39 and the sync output at Pin 7 appear on the scope but with slight vibrations on the two waveforms. When it stops, the sync signal disappears but the clock output signal remains and now steady. When after sometime the sync appears again, the two waveforms start start to vibrate slightly again.

I have connected back all the wires to the other chips.

My power-on-reset: A combination of an inverter & one short works well.

I have mapped my blank Rom (2732) chip to the memory space F000 - 7FFF selected by /7Y on the decoder chip. The RAM (6116) mapped to the memory space 0000 - 07FF selected by /Y0 on the decoder chip 74LS138.

I am using two VIAs 6522, mapped to memory space A000 - BFFF; both selected by /Y5 on the decoder chip.
I want VIA1 to be mapped to A000 - A00F
and VIA2 to be mapped to A100 - A10F

How do I put the VIAs in the separate spaces above.
Once again, thank you all for your assistanve.

_________________
folorunsoa

I want to correct the eprom memory mapping which should be F000 - FFFF and NOT F000 - 7FFF. Please note. Thanks.

_________________
folorunsoa

I want to add for your information that when the sync signal appears on pin 7 of the 6502 chip, the addresses appear too. And when it disappears, the addresses disappear also. I am so sorry to bother you but the reason is that I am very eager to learn from your experience.
Thanks.

_________________
folorunsoa

The sync output tells when the processor is fetching an op code. Since instructions take anywhere from two to seven clocks each, the sync output definitely won't be an evenly spaced pulse output in normal running.

To get your VIAs at addresses A000 and A100, run A8 directly to one of the VIAs' CS1 input, and take the same A8 through an inverter to run to the other VIA's CS1 input. Leave the CS2\ inputs just the way you have them.

But actually you don't need the '138. You can do all your address decoding, including gating the RAM with phase 2 as you need to for dependable operation, all with just a 74HC00 quad NAND, as in http://www.6502.org/users/garth/project ... hematic=17
. (I used the fourth NAND section in the reset circuit. Ideally that reset circuit should use a gate with a Schmitt-trigger input, but I guess I forgot to use the '132, and the high gain of the CMOS logic plus the CMOS processor's Schmitt-trigger reset input have made it work right all these years that I didn't notice my mistake.)

Notice there's not even a separate clock oscillator on this one. Using the CMOS 6502 (65c02) instead of NMOS, you can just hang a resistor and capacitor on the clock pins if the speed is not critical. It can also have a crystal connected directly. The CMOS 6502's Schmitt-trigger reset input even allows you to put an RC there if you want to, instead of a separate timer circuit. The CMOS ones has the bugs fixed, has added instructions, allows the clock to be stopped, takes far less power, is faster, can drive heavier busses, etc., etc..

You can see the same address-decoding idea extended to more I/O ICs at http://www.6502.org/users/garth/project ... chematic=2 . You could have up to 10 of these plus RAM and ROM using only the 74xx00.

Garth

Is your 2732 actually blank (as in filled with $FF's)?

If so, your processor is most likely reading the reset vector and jumping to address $FFFF, where its finding the opcode $FF (which is an undefined instruction on the 6502). It may be treating it as a NOP, which will cause the processor to increment the address register and wrap around to $0000. Now, it will be reading RAM which most likely contains random values on power-up.

You need to burn a test program of some sort into your ROM in order to test it properly.

If you have a test program loaded, please post it so we can help determine what might be happening.

Thanks!

Daryl

Thank you Garth. I checked your earlier project with the url given and I must say I was impressed with the fact that one could use a nand gate instead of -138 for decoding. I was surprised that you used nand gates to decode all the ICs in the Bench-1 illustrations. Please I need some tutorials on this nand gate decoding process. For example, you chose Address A8 and /A8 to separate my two VIAs. Why did you choose A8 and not A7 or A9 or any of the other addresses? Could you please use your illustrations in Bench-1 to further explain to me.
Thanks also for the advantages of the CMOS 6502 over the NMOS type highlighted in your submission. I may have to shift over to the CMOS version in my future designs when I get more confident.

Now Daryl, burning a test program is another problem I want to put across to forum members. I have a Sunshine (Citadel) 60/80 Programmer. The software for the programmer which was installed on my older PC got crashed with the hard drive. Unfortunately, the diskettes that came with the programmer are no longer accessible for any reinstallation to be made. Could any member help me with the programmer software? Also my PC now runs on Windows XP. I have downloaded the tasm.exe software on it but would not run. Each time I tried to run it, I got error messages. I therefore need your help to be able to run the tasm on my PC.
Thanks once again.

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folorunsoa

I'm not sure about tasm on Windows XP. You can also try TASS or the built-in assembler used with Mike Kowalski's simulator.

My website is:
http://users.softcom.net/darylr

TASS is at the bottom of the "downloads" tab.


Mike's site is:
http://home.pacbell.net/michal_k/6502.html

If you need help burning the ROM, I can give it a try on my burner. Its a cheap E-Bay burner but has worked for my chips.

Hope that helps.

Daryl

The A8 and A8\ was only for your wanting to put the two VIAs at addresses $100 apart. Using your '138, you'll use the top three address lines to get the A000-BFFF address space; but the $100 is selected with A8. Similarly, a $80 difference would be selected by A7, $40 by A6, etc.. Even if you still want to use your '138 and have your VIAs on Y5\, you really would not need the inverter to select one VIA when A8 is high and the other is low. To simplify, you could just connect one VIA's CS1 to, say, A7, and the other VIA's CS1 to A8, and omit the inverter. Then the base addresses would be $A080 and $A100. If for some unusual reason you wanted to write the same data to both VIAs at once, like to set them both up the same way or start their timers simultaneously, you would write to $A180+the register number.


It uses A15 to select between ROM and everything else. That leaves 32KB of ROM space, regardless of whether or not you use it all. You could still do it this way for an 8Kx8 or a 2Kx8 ROM for example.

If it's not ROM, it uses A14 to select between RAM and I/O. If it's RAM, it gates it with phase 2. The scheme leaves 16KB available for RAM. In my case, I needed more ROM than RAM, so I have a 32KB ROM, but I'm only using half of a 32KB RAM (since commonly available RAM ICs jump from 8KB to 32KB, skipping the 16KB). With a small change, you could get 16KB of ROM and 32KB of RAM.

If A15 and A14 point to the I/O space and all the common I/O ICs have two select lines, you use the next address lines, one to each IC, to select which I/O IC you want to address, leaving just enough at the bottom for the register selects. The 6532 RIOT needs 7 or 8 register-select lines IIRC, but there's not much sense in using a 6532 if you have 6522's and separate RAM available. The 6522's need 4 register-select lines and the 6551's need even fewer (2); so if you use A0-A3 for register selects, all the address lines between A3 and A14 (non-inclusive) can be used for chip selects. That's ten.

I hope this is clear. It is common for newcomers to make the glue logic much more complex than it needs to be, requiring more board space, more time to build, and longer total propagation delays which limit the maximum speeds.

You could try here ..

http://www.danbbs.dk/~rmadrm/sunshine.htm

.. this seems to be the only Sunshine software site around.

Lee.