Hello folks, new member and first post here. This might go better in Newbies, but I'm going to focus on hardware, so here we are...

I got into computers when my dad built a COSMAC Elf II kit, and began I programming in 1802 machine language on graph paper. He and I soon moved on the the 6502, and SBC computers, then the Apple ][ and Macintosh. I got sidetracked into writing Computer Based Training software for CDC PLATO and related ports of Tutor on various mini and microcomputers. I learned UNIX along the way, and ultimately did a lot of system support and network administration for various companies. Nowadays I do system support and special projects for a private university. In my so-called spare time, I teach mechatronics and Arduino programming for our local Hackerspace. But I never forgot my early experience with single-board computers, and for some reason now is the time to come full circle and scratch that itch again.

I've been lurking for a while now, and reading data sheets and Garth Wilson's excellent hardware primer, and I've come up wth a concept for what I want to build. I freely admit that what I'm doing is idiosyncratic, and not the easy way, but I'm having fun so far, and at least it will be unique! My goals for the project are the following;

• Play with 6502s!
• Blinkie lights!
• Eventually drive an electrostatic vector CRT.
• Stay away from Arduino and other advanced micro controller ecosystems.
• Stay away from SMT and FPGAs. (for now)

Following those goals, I've made some decisions about the initial configuration I want to build. I'll be designing around WDC's W65C02S and not worrying about compatibility with Rockwell or CMD/MOS devices. I/O will initially include a WDC W65C22 VIA and a W65C51N ACIA, with addressing space for future VIAs and DACs. Clock speed will be a modest 1.0 MHz to start. Glue logic will be discrete 74HCXX. The configuration will be ROMless, using a supercap-backed Cypress CY62256N SRAM in the lower 32K, mirrored into the the upper 32K to cover the vector address space. I/O addressing is also in the upper 32K.

$C000 - $FFFF RAM (mirrored)
$A000 - $AFFF 6522 VIA
$9000 - $9FFF 6551 ACIA
$0000 - $7FFF RAM

The major goal of the initial configuration is to design and build a proper dead start panel, similar to the one in the Altair 8800. (Thus the name in the subject!) No, it's not practical. But it is an interesting design challenge, and once I load a bootstrap into the RAM, I can graduate to a serial terminal pretty quickly after. Having used the crude switch panel on the Elf, I know a panel with a deposit/next function will be quite a bit less painful. It's also a great excuse to really dig into the details of interfacing to the 6502. I'm generally modeling the panel on the Altair 8800's, but the CMOS bus and different timing and instruction set permits me only to use the design concept rather than any of that circuit. Initially, interrupts won't be used, and reset will be handled by a DS1813 for simplicity. I expect to breadboard a good deal of the initial rev, then move on to wire wrap or a PCB ( I haven't decided.)

That's probably enough for now -- comments, questions, scathing rebuttal?

-- Mike Bakula

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Welcome!
This looks interesting.
I was originally going to do something sort of like this, except I planned to have an EEPROM in there, and program that using the front panel(to try and save buying an EEPROM blaster). I quickly figured out that the front panel would be an absolute pig to build on a plug-in breadboard, not to mention difficult to design. I ended up abandoning that approach, and just getting an EEPROM programmer.
That said, I have far less experience than you do, so don't let me stop you!

There is definitely a certain charm to a front panel. Seeing the binkenlichten going can be cool, but 1 MHz may ruin the effect somewhat. I say this from experience, having made a test program to output a binary count-up on a VIA port, only to have most of it so fast as to be indistinguishable from full-time lit. I even had a count-to-255 delay in there(It was made with an INC A, though, and not an ADC, so it isn't the slowest of delays).

Like Mr. WIlson, I would suggest that you wire up the IRQ lines appropriately at the start, as it could be a pain to do it later on, especially if you use wires under a pad-per-hole PCB like I did. I tried to use the 16V8 in mine to combine the VIA and ACIA IRQ lines(the ACIAs have open-collector IRQs. The VIAs have totem-pole ones). The PLD did not play ball, so I ended up using a 1N5711 Schottky diode facing into the VIAs IRQ output, to nullify its pull-up ability. You can use an AND gate instead, if you have one spare. You don't have to use the IRQs initially. As far as I know, they're all disabled by default.

Ok, I can see that - as you say, the addition is trivial. I expect I'll be using /NMI later for the CRT interface, but I don't need it for the deadstart panel.

The design of the dead start panel is a more interesting problem than I thought at first. Just halting the processor and addressing the memory directly via switches is possible, but as many have commented before, tedious and error-prone. What the Altair does is lie to the microprocessor, using it as a presettable counter to do memory addressing in a more user friendly way. The two 8-bit banks of switches are fed via tristate buffers to the data bus, not the address bus. With the machine halted and an address on the switches, the examine switch enables a clock which feeds a 2-bit counter. The counter drives a 2 to 4 decoder, which gates a hardwired JMP opcode, the low byte and the high byte switches to the data bus in turn and clocks the microprocessor. At the end of the sequence, it returns to halt. The examine next merely gates a NOP to the processor, and clocks it. Deposit merely enables the low switch bank and toggles the RAM's write line. It's actually very clever, and while not simple, I think fairly straightforward to design. Counting cycles isn't even too much of a problem, since the SYNC line tells us when an instruction is complete.

There are a number of details to sort out, which is where I'm at on the project right now. The Altair uses a separate multivibrator for the dead start panel clock -- I think I'll go ahead and use phi2, but gated separately so it doesn't go to the peripherals. The Altair also does things with open collector outputs that I'll be doing with tristate buffers, so there's some steering logic to figure out.

Hi,

Instead of the CY RAM and supercap I might suggest http://www.mouser.com/ProductDetail/STMicroelectronics/M48Z35Y-70PC1/?qs=sGAEpiMZZMvaNBfR%2fsmQG3q6CQ8OY03uUePeJGogy98%3d as an alternative. More expensive but simple and very handy.

Several years ago I had started a project very much like this. I don't know that I'll ever finish it though; I have no time to devote to it. The only part I did finish is the most trivial: the rack mount case and front panel, hardware only. I wonder you'd be interested in what I have.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I like the idea where the 6502 is used to control the address, so you don't need switches for that. The challenge is to come up with the simplest design possible.

As a teenager I wanted to build a COSMAC ELF because it was almost affordable to 15 year old me. One of the things I liked about it was the built in DMA mode which eliminated the address switches entirely. It was also a relatively simple matter to add a hex keypad like the ELF II.

So I wonder if something similar could be pulled off with a bidirectional counter and the BE line of the 6502. Basically you suspend the processor and use the counter to enter bytes sequentially from FFFF downwards. That way you can enter all the vectors followed by the code.

At reset- or on an interrupt - the 6502 fetches an address from high memory. If the front panel controls the address bus for the two crucial cycles, then the same 8 switches can provide an initial address. If subsequent instruction fetches cause the 6502 to see a NOP, but cause the memory to see a write, with data from the same switches, then you can input your program sequentially, using the 6502 as a counter, and with no need for 16 address input switches.

Nice idea. Now, instead of feeding the CPU NOPs, can you come up with a clever sequence of instructions that can be executed while you enter them ? That would make it even simpler.

While simpler, I think having the ability to set the PC register is handy, and then you don't have to worry about managing address lines - once you add a separate address counter, what you see on the lines is a bit removed from the processor. I think the extra effort to control the processor is a better tradeoff.

The idea of using resistor coupling on the bus lines is a handy one, regardless -- it makes the design more modular.


This is an interesting idea. You do have to watch for side effects; interrupt will push the stack, and you don't want to be doing that repeatedly. Reset however, may work for this. Will that simplify the clocking vs. grabbing the bus and forcing a JMP?

When doing examine/next or write/next, I think you want to stick to NOP, for the same reasons; you want to minimize side effects on the processor state, since it's a bunch of logic to recover or reset it.

KC9UDX, that's a nice panel, but I have access to a laser cutter/engraver, so I'm planning to do my panel out of red acrylic. As an aside, I'm looking for a source for some NKK paddle switches, the M2012TNW03-EC. Nobody seems to stock them. I know the imsai.net folks have vintage paddle switches, but I'm not building a reproduction.

There's a tradeoff here between having 16 switches and doing some steering logic, or using 8 and single stepping. With 8, doing an examine takes three steps instead of two(examine, ADL, ADH), but it's really the same number of switch settings. Is this a difference that makes a difference?

For the NKK switches, I found this: http://uxpro.com/shop/index.php?route=product/product&product_id=65.

Alternatively, Oscar Vermeulen has (I think) a lead on some nice switches that he wants to use for his PDP-11 replica: http://obsolescenceguaranteed.blogspot.no/2016/01/starting-to-make-pidp-1170.html

Hmm. Rather than counting, isn't what we really want to do (for the 16-switch concept) sequencing? Why not just clock a bit across a shift register to do the chip selects in turn? Then preset the shift register on SYNC.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?