akohlbecker wrote:
That is quite curious. I'm using RDY with Ben Eater's VGA card kit to stop the CPU during the display phase, and it is working properly. The card is asserting/de-asserting RDY and BE at the same time (they are connected together) on the falling edge of the CPU clock.
A careful look at the datasheet reveals there's a fairly wide timing window (relative to the 65xx CPU clock) during which it's safe to change the state of RDY. But there's also a comparatively brief interval (defined by tPCS and tPCH) during which RDY must remain stable -- either high or low, but not in transition. More on that in
this post.
As I recall, Gordon's unsuccessful experiment drove the RDY pin with a signal derived from a separate processor that used a separate clock source. The independent clock source introduces a random element, making it possible that RDY may change at any time within the 65xx clock cycle. This means that tPCS and tPCH would occasionally get violated, with the accompanying risk that the processor will go off into the weeds.
Your own project does not involve a separate clock, so that random element is absent. RDY always changes state at a certain time within the 65xx cycle, and apparently the circuit you've chosen is such that tPCS and tPCH requirements are met.
PS- Congrats on the PCB's!
-- Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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Just in time for some week-end soldering.
